Design and implementation of a time-division multiplexing scan architecture using serializer and deserializer in GPU chips

@article{Sanghani2011DesignAI,
  title={Design and implementation of a time-division multiplexing scan architecture using serializer and deserializer in GPU chips},
  author={Amit Sanghani and Bo Yang and Karthikeyan Natarajan and Chunsheng Liu},
  journal={29th VLSI Test Symposium},
  year={2011},
  pages={219-224}
}
We present the design and implementation details of a time-division demultiplexing/multiplexing based scan architecture using serializer/deserializer. This is one of the key DFT features implemented on NVIDIA's Fermi family GPU (Graphic Processing Unit) chips. We provide a comprehensive description on the architecture and specifications. We also depict a compact serializer/deserializer module design, test timing consideration, design rule and test pattern verification. Finally, we show silicon… CONTINUE READING
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