Design and evaluation of Avalon compatible adapter and parameterizable NoC router for FPGAs

Abstract

Rapid improvements in integrated circuit technology over the past few decades enable increasingly large and complex Field Programmable Systems-on-Chip (FPSoC). Due to the large number of components used, the traditional bus-based interconnect scheme becomes cumbersome and restrictive. Hence, the Network-on-Chip (NoC) interconnect paradigm becomes appealing due to its many advantages such as scalability and superior performance. In this paper, we describe the design and evaluation of two major NoC components: a flexible adapter compatible with the Altera Avalon interconnect standard and a parameterizable wormhole router. The Avalon compatible adapter will be very useful to NoC designers using IP cores provided by Altera to implement NoC-based systems on Altera FPGAs. The design space of these components was explored by synthesizing them for an Altera Stratix II FPGA for different values of channel width. The effects of varying channel width on area, power and clock frequency of these components were explored. Experimental results show that a channel width of 16 bits gives the best tradeoff for optimizing area, power and clock frequency.

DOI: 10.1109/CCECE.2015.7129335

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Cite this paper

@article{Murawski2015DesignAE, title={Design and evaluation of Avalon compatible adapter and parameterizable NoC router for FPGAs}, author={Matthew Murawski and R. M. Jenita Priya and Mohammed Khalid}, journal={2015 IEEE 28th Canadian Conference on Electrical and Computer Engineering (CCECE)}, year={2015}, pages={553-558} }