In advanced wireless communication, Turbo codes play a crucial role in different applications, such as mobile radio, computerized video, long-haul terrestrial wireless satellite communications, deep space communication and military applications and so on. The turbo codes are designed with the help of Recursive Systematic Convolutional and are separated by interleaver, which (component used to rearrange the bit sequence) plays a vital role in the encoding process. This paper provides the design of a Turbo Encoder, which is parallel concatenation of Recursive Systematic Convolutional (RSC) encoders and interleaver to reduce delay. The Turbo Encoder is designed by Verilog-HDL and Synthesized by Xilinx ISE. Further its performance is analyzed through evaluation of metrics such as area and delay.