Design of speed and power efficient multipliers using Vedic Mathematics with VLSI implementation”IEEE2014
- S. Patil
Now a days security is the prime part for both, the satellites communication of the electronics data and the stored data, hence encryption is important for information processing system and communication network. In this paper the designed of AES cryptography are develop by the direct method of computing the discrete linear convolution of finite length sequence. The proposed approach is easy to learn due the use of speed efficient Vedic multiplier. Since it minimize the execution time and area, so the delay and power consumption is further decrease by the compact and flexible approach in the Mixcolumn transform which takes different approach rather than conventional multiplication previously used in AES. Model process applied in this paper is bottom-up approach. The structure style of modeling helps to easy understandable the proposed design of algorithm. AES is the symmetrical 128 bit has designed and verified in the Verilog HDL in Xilinx 14.7 tool.