Design and analysis of a 20-GHz clock multiplication unit in 0.18-/spl mu/m CMOS technology

@article{Lee2005DesignAA,
  title={Design and analysis of a 20-GHz clock multiplication unit in 0.18-/spl mu/m CMOS technology},
  author={Jri Lee and Shanghann Wu},
  journal={Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005.},
  year={2005},
  pages={140-143}
}
A 20-GHz clock multiplication unit for SONET OC-768 systems employs dual loops and third-order loop filter to suppress the jitter. Realized in 0.18-/spl mu/m CMOS technology, this circuit achieves an output jitter of 0.2 ps,rms and 4.5 ps,pp while consuming 40 mW from a 1.8-V supply. 

Citations

Publications citing this paper.
Showing 1-4 of 4 extracted citations

A 1.2-V 37–38.5-GHz Eight-Phase Clock Generator in 0.13- $\mu$m CMOS Technology

IEEE Journal of Solid-State Circuits • 2007
View 9 Excerpts
Highly Influenced

A 1.2V 37-38.5GHz 8-Phase Clock Generator in 0.13/spl mu/ m CMOS Technology

2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. • 2006
View 2 Excerpts

References

Publications referenced by this paper.
Showing 1-6 of 6 references

A 20-Gb/s 2-to-1 MUX and a 40-GHz VCO in 0.18- m CMOS Technology

Jri Lee
submitted to the 2005 Symposium on VLSI Circuits. • 2005
View 1 Excerpt

A 40-GHz frequency divider in 0.18-/spl mu/m CMOS technology

IEEE Journal of Solid-State Circuits • 2004
View 1 Excerpt

40 43-Gb/s OC-768 16:1 MUX/CMU Chipset with SFI-5 Compliance

Hai Tao
IEEE J. Solid-State Circuits, vol. 38, pp. 2169-2180, Dec. 2003. • 2003
View 2 Excerpts

A 0.18- m SiGe BiCMOS Receiver and Transmitter Chipset for SONET OC-768 Transmission Systems

Mounir Meghelli
IEEE J. Solid-State Circuits, vol. 38, pp. 2147-2154, Dec. 2003. • 2003
View 1 Excerpt

A Si Bipolar Phase and Frequency Detector IC for Clock Extraction up to 8 Gb/s

A. Pottbacker
IEEE J. Solid-State Circuits, vol. 27, pp. 1747-1751, Dec. 1992. In a redesign, the VCO frequency should be raised by . Fig. 10. Output spectrum under locked condition. Technology 0.18−um CMOS Output Freq. 20 GHz Multiply Ratio 32 Clock Jitter 0.2 ps,rms < 4.5 ps,pp Power Diss. 40 mW Supply 1.8 V C • 1992
View 1 Excerpt

Similar Papers

Loading similar papers…