Design and Verification of a Stack Processor Virtual Component


0272-1732/01/$10.00  2001 IEEE Application-specific integrated circuit (ASIC) design is undergoing major changes. As single-chip functionality continuously increases and becomes more specialized, systems on a chip (SOCs) become a reality. However, competition and technological needs demand shorter product development cycles, consequently raising several issues for ASIC designers. To increase productivity, designers devise fairly general building blocks, or virtual components (VCs), from which various ASIC architectures are then designed. However, to warrant multiple reuse of a VC in various applications, its functionality and interfaces must be extensively parameterizable and customizable. Incorporating VCs exacerbates the difficulties designers face when ensuring that very large-scale integration (VLSI) circuits function as intended. High circuit complexity (in terms of high overall gate count, massive node to pin ratio, and thousands of test vectors), missing or unaffordable information about VC internal details, and unforeseen interactions between VC parameter settings all contribute to problems with functional verification. According to estimates, functional verification is now between one third and one half of the total IC design effort. Providing VC users with self-configurable—and hence, reusable—test benches would prevent verification from consuming disproportionate amounts of engineering time. It makes little sense, though, to reuse VCs if their test benches require designers to manually rewrite VCs for every application. Inclusion of an application-specific instruction set processor (ASIP) implements fixed and highly repetitive computational tasks in hardware. Software handles tasks that are irregular or likely to be modified. This approach effectively combines applicationspecific functionality with a limited, yet needed degree of flexibility in a single design. An ASIP-customizable instruction set provides designers with even more latitude in finding the best performance and area trade-offs. Yet Manfred Stadler Markus Thalmann

DOI: 10.1109/40.918004

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@article{Stadler2001DesignAV, title={Design and Verification of a Stack Processor Virtual Component}, author={Manfred Stadler and Markus Thalmann and Thomas R{\"{o}wer and Hubert Kaeslin and Norbert Felber and Wolfgang Fichtner}, journal={IEEE Micro}, year={2001}, volume={21}, pages={69-80} }