Design and Verification of Low Power SRAM using 8T SRAM Cell Approach

  title={Design and Verification of Low Power SRAM using 8T SRAM Cell Approach},
  author={N. Rahman and B. Singh},
  journal={International Journal of Computer Applications},
  • N. Rahman, B. Singh
  • Published 2013
  • Computer Science
  • International Journal of Computer Applications
  • SRAM cell stability will be a primary concern for future technologies due to variability and decreasing power supply voltages. Advances in chip designing have made possible the design of chips at high integration and fast performance. Lowering power consumption and increasing noise margin have become two central topics in every state of SRAM designs.The Conventional 6T SRAM cell is very much prone to noise during read operation. To overcome the read SNM problem in 6T SRAM cell, researchers have… CONTINUE READING
    13 Citations
    Performance Analysis of 6T SRAM Cell on Planar and FinFET Technology
    • A. A. Kumar, Anu Chalil
    • Computer Science
    • 2019 International Conference on Communication and Signal Processing (ICCSP)
    • 2019
    • 2
    Performance analysis of 22NM FinFET-based 8T SRAM cell
    Design of a low-power average-8T SRAM cell using transmission gate
    • N. Vinitha, K. Kavitha
    • Computer Science
    • 2017 Third International Conference on Science Technology Engineering & Management (ICONSTEM)
    • 2017
    Analyzing the Impact of Sleep Transistor on SRAM
    • 2
    • PDF
    Review on Performance of Static Random Access Memory (SRAM)
    • 2
    Review on Performance of Static Random Access Memory (SRAM)


    Variation tolerant 9T SRAM cell design
    • 16
    Stable SRAM cell design for the 32 nm node and beyond
    • L. Chang, D. Fried, +9 authors W. Haensch
    • Engineering, Computer Science
    • Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005.
    • 2005
    • 537
    • PDF
    A read-static-noise-margin-free SRAM cell for low-VDD and high-speed applications
    • 261
    Static Noise Margin of 6T SRAM Cell in 90-nm CMOS
    • 36
    Read Stability and Write-Ability Analysis of SRAM Cells for Nanometer Technologies
    • 387
    • PDF
    Static noise margin variation for sub-threshold SRAM in 65-nm CMOS
    • 305
    • PDF
    Static-noise margin analysis of MOS SRAM cells
    • 1,340
    • PDF
    Increasing static noise margin of single-bit-line SRAM by lowering bit-line voltage during reading
    • 13
    A read-static-noise-margin-free SRAM cell for low-V/sub dd/ and high-speed applications
    • K. Takeda, Y. Hagihara, +4 authors H. Kobatake
    • Computer Science
    • ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005.
    • 2005
    • 234