Design and Verification Languages

@inproceedings{Edwards2004DesignAV,
  title={Design and Verification Languages},
  author={Stephen A. Edwards},
  year={2004}
}
After a few decades of research and experimentation, registertransfer dialects of two standard languages—Verilog and VHDL—have emerged as the industry standard starting point for automatic large-scale digital integrated circuit synthesis. Writing RTL descriptions of hardware remains a largely human process and hence the clarity, precision, and ease with which such descriptions can be coded correctly has a profound impact on the quality of the final product and the speed with which the design… CONTINUE READING