Design and VLSI implementation of a Low Probability of Error Viterbi Decoder

  title={Design and VLSI implementation of a Low Probability of Error Viterbi Decoder},
  author={C. Arun and V. Rajamani},
  journal={2008 First International Conference on Emerging Trends in Engineering and Technology},
The use of error-correcting codes has proven to be an effective way to overcome data corruption in digital wireless communication channels, enabling reliable transmission to be achieved over noisy and fading channels. In this paper a novel approach to design a high throughput with reduced bit error probability Viterbi decoder is described and implemented. Low bit error rate (BER) can be achieved by increasing the free distance (dfree) of the Viterbi decoder without increasing complexity. The… CONTINUE READING
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  • We have also achieved a high speed (84.958 Mbps) and low Bit Error Rate (BER) viterbi decoder.


Publications referenced by this paper.
Showing 1-10 of 15 references

Implementation of scalable power and area efficient highthroughput Viterbi decoders,

  • T. Gemmeke, M. Gansen, T. Noll
  • IEEE J. Solid-State Circuits,
  • 2002
3 Excerpts

Reconfigurable Computing and Digital Signal Processing: A Survey

  • R. Tessier, W. Burleson
  • Journal of VLSI Signal Processing, Vol.28,
  • 2001
1 Excerpt

Low-power Viterbi decoder for CDMA Mobile Terminals, “Conference-Paper; Journal-article

  • Kang, A. N. Willson
  • IEEE-Journalof- Solid-State-Circuits. Vol.33,
  • 1998
1 Excerpt

Low Power Soft Output Viterbi Decoder Scheme for Turbo Code Decoding,

  • L. Lang, C. Y. Tsui, R. S. Cheng
  • Proc. Int. Symp. On Circuits and Systems,
  • 1997
2 Excerpts

IC Design of an Adaptive Viterbi Decoder,

  • M-H Chan, W-T Lee, M-C Lin, L-G Chen
  • IEEE Trans. on Consumer Electronics,
  • 1996
2 Excerpts

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