Design and VLSI implementation of a Low Probability of Error Viterbi Decoder

@article{Arun2008DesignAV,
  title={Design and VLSI implementation of a Low Probability of Error Viterbi Decoder},
  author={C. Arun and V. Rajamani},
  journal={2008 First International Conference on Emerging Trends in Engineering and Technology},
  year={2008},
  pages={418-423}
}
The use of error-correcting codes has proven to be an effective way to overcome data corruption in digital wireless communication channels, enabling reliable transmission to be achieved over noisy and fading channels. In this paper a novel approach to design a high throughput with reduced bit error probability Viterbi decoder is described and implemented. Low bit error rate (BER) can be achieved by increasing the free distance (dfree) of the Viterbi decoder without increasing complexity. The… CONTINUE READING
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  • We have also achieved a high speed (84.958 Mbps) and low Bit Error Rate (BER) viterbi decoder.

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