Design and Simulation of Low Dropout Regulator

Abstract

The proposed CMOS Low Dropout (LDO) regulator has been designed and simulated using TSMC 0.25μ CMOS process in cadence analog design environment . This paper illustrates the design criteria and corresponding analysis relevant to LDO. The experimental result shows that, it regulates an output voltage at 3.3V from a 3.5V supply, with a minimum dropout voltage of 200mV at a maximum output current of 50mA using a reference voltage of 1.2V. The regulator provides a load regulation of 0.092V/A, line regulation of 0.16mV/V. Efficiency of 93.27% is achieved. Detailed analysis of CMOS LDO has been presented.

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Cite this paper

@inproceedings{Kumar2015DesignAS, title={Design and Simulation of Low Dropout Regulator}, author={C. Sathish Kumar and K. V. Sujatha}, year={2015} }