Design and Sensitivity Analysis of a New Current-Mode Sense Amplifier for Low-Power SRAM

Abstract

A new current-mode sense amplifier is presented. It extensively utilizes the cross-coupled inverters for both local and global sensing stages, hence achieving ultra low-power and ultra high-speed properties simultaneously. Its sensing delay and power consumption are almost independent of the bitand data-line capacitances. Extensive post-layout simulations, based on an industry standard 1 V/65-nm CMOS technology, have verified that the new design outperforms other designs in comparison by at least 27% in terms of speed and 30% in terms of power consumption. Sensitivity analysis has proven that the new design offers the best reliability with the smallest standard deviation and bit-error-rate (BER). Four 32 32-bit SRAM macros have been used to validate the proposed design, in comparison with three other circuit topologies. The new design can operate at a maximum frequency of 1.25 GHz at 1 V supply voltage and a minimum supply voltage of 0.2 V. These attributes of the proposed circuit make it a wise choice for contemporary high-complexity systems where reliability and power consumption are of major concerns

DOI: 10.1109/TVLSI.2009.2033110

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Cite this paper

@article{Do2011DesignAS, title={Design and Sensitivity Analysis of a New Current-Mode Sense Amplifier for Low-Power SRAM}, author={Anh-Tuan Do and Zhi-Hui Kong and Kiat Seng Yeo and Jeremy Yung Shern Low}, journal={IEEE Trans. VLSI Syst.}, year={2011}, volume={19}, pages={196-204} }