Design and Performance of SMPs With Asynchronous Caches

@inproceedings{Pong1999DesignAP,
  title={Design and Performance of SMPs With Asynchronous Caches},
  author={Fong Pong and Michel Dubois and Ken Lee},
  year={1999}
}
Asynchronous, cache coherence, shared-memory multiprocessor, SMP We propose and evaluate a cache-coherent symmetric multiprocessor system (SMP) based on asynchronous caches. In a system with asynchronous caches, processors and memory controllers may observe the same coherence request at different points in time. All protocol transactions are unidirectional and processors do not report snoop results. The need for an extensive interlocking protocol between processor nodes and memory controller… CONTINUE READING
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