Design and Performance analysis of efficient bus arbitration schemes for on-chip shared bus Multi-processor SoC

Abstract

In the resource sharing mechanism of multi-processor SoC, the on-chip communication architecture plays an important role and directly affects the performance of SoC. The traditional shared bus arbitration schemes show the several defects such as bus starvation, and low system performance. In this paper, we discuss about the static & dynamic Lottery Bus… (More)

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Cite this paper

@inproceedings{Doifode2008DesignAP, title={Design and Performance analysis of efficient bus arbitration schemes for on-chip shared bus Multi-processor SoC}, author={Neeta Doifode and Dinesh Padole and Dr and Preeti R. Bajaj}, year={2008} }