Design and Implementation of a Secure RISC-V Microprocessor

@article{Stangherlin2022DesignAI,
  title={Design and Implementation of a Secure RISC-V Microprocessor},
  author={Kleber Stangherlin and Manoj Sachdev},
  journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
  year={2022},
  volume={30},
  pages={1705-1715}
}
  • K. StangherlinM. Sachdev
  • Published 10 May 2022
  • Computer Science
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Secret keys can be extracted from the power consumption or electromagnetic emanations of unprotected devices. Traditional countermeasures have a limited scope of protection and impose several restrictions on how sensitive data must be manipulated. We demonstrate a bit-serial RISC-V microprocessor implementation with no plain-text data. All values are protected using Boolean masking. Software can run with little to no countermeasures, reducing code size and performance overheads. Unlike previous… 

Secure and Lightweight Strong PUF Challenge Obfuscation with Keyed Non-linear FSR

A secure and lightweight key based challenge obfuscation for strong PUFs designed to be resilient against learning attacks and the cost of protecting the architecture against power analysis attacks with clock randomization, and Boolean masking is discussed.

References

SHOWING 1-10 OF 54 REFERENCES

Protecting RISC-V against Side-Channel Attacks

This work made use of state of the art masking techniques and presented a novel solution to protect memory access against SCA by integrating side-channel analysis countermeasures into a RISC-V implementation, protecting against first-order power or electromagnetic attacks while keeping the implementation costs as low as possible.

Sharing is Caring - On the Protection of Arithmetic Logic Units against Passive Physical Attacks

This work investigates how to counteract first-order passive physical attacks on an embedded microcontroller with the provably secure threshold implementation TI masking scheme, and focuses on the protection of the central point of data processing in the microcontroller design--the arithmetic logic unit ALU.

Combinational Logic Design for AES SubByte Transformation on Masked Data

  • E. Trichina
  • Computer Science, Mathematics
    IACR Cryptol. ePrint Arch.
  • 2003
This paper describes an attempt to embed data masking technique at a hardware design level for an AES coprocessor, and focuses on inversion in GF since it is the only non-linear operation, and requires complex transformations on the masked data and masks.

Domain-Oriented Masking: Compact Masked Hardware Implementations with Arbitrary Protection Order

This talk demonstrates how the costs for protecting digital circuits against passive physical attacks can be lowered significantly and introduces a novel masking approach called domain-oriented masking (DOM), which provides the same level of security as threshold implementations (TI), while it requires less chip area and less randomness.

TEL Logic Style as a Countermeasure Against Side-Channel Attacks: Secure Cells Library in 65nm CMOS and Experimental Results

Experimental results have shown a strong reduction of the information leakage with respect to the sense amplifier based logic logic style under mismatched load conditions with an improvement in the measurements to disclosure of more than three orders of magnitude.

Design of Adiabatic Dynamic Differential Logic for DPA-Resistant Secure Integrated Circuits

This work proposes the implementation of adiabatic dynamic differential logic (ADDL) for applications in secure integrated circuit (IC) design, and presents a high-performance ADDL and a body-biased ADDL for ultralow power applications.

Randomized Multitopology Logic Against Differential Power Analysis

Theoretical analysis and simulation results clearly show higher immunity to DPA attacks when using the proposed RMTL approach compared with standard CMOS implementation.

Differential Power Analysis

Methods for analyzing power consumption to get the secret keys are examined and the ways for building systems that can operate safely using existing hardware, which leaks information are discussed.

Generic Low-Latency Masking in Hardware

A generalized concept for low-latency masking that is applicable to any implementation and protection order, and (in its most extreme form) does not require on-the-fly randomness is introduced.

Concealing Secrets in Embedded Processors Designs

The research on masking as a countermeasure against side-channel analysis attacks focuses merely on cryptographic algorithms, and has either been implemented for particular hardware or software implementations.
...