Corpus ID: 59902085

Design and Implementation of a 1.2 Gbit/s ATM Cell Buffer using a Synchronous DRAM chip

@inproceedings{Glykopoulos1998DesignAI,
  title={Design and Implementation of a 1.2 Gbit/s ATM Cell Buffer using a Synchronous DRAM chip},
  author={George N. Glykopoulos},
  year={1998}
}
High speed networks require high throughput memories to store cells or packets. Synchronous Dynamic RAM (SDRAM) chips provide both high storage capacity and high throughput, and are thus an appropriate technology for building such cell or packet buffers. One 16Mbit SDRAM chip with a 16-bit data interface provides 40K cell storage and 1.2Gbit/s throughput when used as an ATM cell buffer. The purpose of this work is to demonstrate this capability in a working prototype, gaining familiarity with… Expand
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