Design and Implementation of Viterbi Decoder with FPGAs

@article{Kivioja1999DesignAI,
  title={Design and Implementation of Viterbi Decoder with FPGAs},
  author={M. Kivioja and Jouni Isoaho and L. V{\"a}nsk{\"a}},
  journal={VLSI Signal Processing},
  year={1999},
  volume={21},
  pages={5-14}
}
In this paper we present our studies for implementing complex DSP and Telecom systems in FPGAs. We analyse suitability of FPGA device architectures for implementing complex algorithms. Here we use a Viterbi algorithm as a deeper case study. Different architectural strategies for implementations are discussed and analysed with the special emphasis on practical FPGA implementations. Speed performance, easy routability and minimisation of inter-chip communication are used as design criteria… CONTINUE READING

References

Publications referenced by this paper.
Showing 1-10 of 11 references

DSP system implementation with synthesis based design automation,

  • I. Harjunpää
  • M.Sc. thesis, Tampere University of Technology,
  • 1995

HLS based DSP Optimization with ASIC RTL libraries,

  • J. Isoaho, J.̈ Oberg, A. Hemani, H. Tenhunen
  • VLSI Signal Processing VII ,
  • 1994

High level synthesis in DSP ASIC optimization,

  • J. Isoaho, J.̈ Oberg, A. Hemani, H. Tenhunen
  • Proc. of 7th IEEE ASIC Conference and Exhibit
  • 1994

Fast implementation of stack filters with VHDL-based synthesis and FPGAs,

  • J. Nousiainen, J. Isoaho, O. Vainio
  • IEEE Winter Workshop on Nonlinear Digital Signal…
  • 1993
1 Excerpt

Source and Channel Coding, an Algorithmic Approach

  • J. B. Anderson, S. Mohan
  • Kluwer Academic Publishers,
  • 1991
2 Excerpts

Fundamentals and Applications. The Aerospace Corporation, El Sequndo, California and University of California

  • B. Sklar, Digital
  • Los Angeles,
  • 1988
2 Excerpts

Memory management in a viterbi decoder,

  • C. M. Rader
  • IEEE Transactions on Communications , Vol. COM…
  • 1981
2 Excerpts

Similar Papers

Loading similar papers…