Corpus ID: 212464274

Design and Implementation of Modified Charge Pump for Phase Locked Loop

@inproceedings{Mano2013DesignAI,
  title={Design and Implementation of Modified Charge Pump for Phase Locked Loop},
  author={M. Mano and G. Selva Priya and K. Sri},
  year={2013}
}
  • M. Mano, G. Selva Priya, K. Sri
  • Published 2013
    • -A PLL is a closed loop system that locks the phase of an output signal to an input reference signal. The term “lock” refers to a constant or zero phase difference between two signals. The components of PLL are the Phase Frequency Detector (PFD), the charge pump (CP), the low pass filter (LPF), and the voltage controlled oscillator (VCO). In which the charge pump has been modified in order to overcome the leakage current. Hence power consumption is reduced through the modified structure. All… CONTINUE READING
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    Design of a CMOS PFD-CP module for a PLL
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    References

    SHOWING 1-10 OF 13 REFERENCES
    The Mixed-Signal Design of PLL with CMOS Technology
    • Sijie Zheng, L. He
    • Engineering
    • 2007 International Symposium on Signals, Systems and Electronics
    • 2007
    • 5
    • PDF
    A new fast locking charge pump PLL: analysis and design
    • 5
    Charge pump with perfect current matching characteristics in phase-locked loops
    • 209
    • PDF
    Design of high-performance CMOS charge pumps in phase-locked loops
    • W. Rhee
    • Engineering, Computer Science
    • ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349)
    • 1999
    • 341
    • PDF
    A 50-GHz Phase-Locked Loop in 0.13-$\mu$ m CMOS
    • 105
    Low voltage low noise open loop automatic amplitude control for voltage-controlled oscillators
    • 3
    Phase frequency detectors for fast frequency acquisition in zero-dead-zone CPPLLs for mobile communication systems
    • 37
    A 21-GHz 8-Modulus Prescaler and a 20-GHz Phase-Locked Loop Fabricated in 130-nm CMOS
    • Y. Ding, K. Kenneth
    • Engineering, Computer Science
    • IEEE Journal of Solid-State Circuits
    • 2007
    • 77
    A 1-MHZ bandwidth 3.6-GHz 0.18-/spl mu/m CMOS fractional-N synthesizer utilizing a hybrid PFD/DAC structure for reduced broadband phase noise
    • 130
    • PDF
    A low phase noise PLL using Vackar VCO and a widelocking range tunable divider for Vband signal generation in 65nm CMOS
    • Analog IntegrCirc Sig Process
    • 2013