Design and Implementation of Integer Dct Architectures for Hevc in Vlsi Technology

Abstract

High Efficiency Video Coding (HEVC) inverse transform for residual coding uses 2-D 4x4 to 32x32 transforms with higher precision as compared to H.264/AVC’s 4x4 and 8x8 transforms resulting in an increased hardware complexity. In this paper, an energy and areaefficient VLSI architecture of an HEVC-compliant inverse transform and dequantization engine is… (More)

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