• Corpus ID: 9189472

Design and Implementation of Full Adder Cell with the GDI Technique Based on 0 . 18 μ m CMOS Technology

  title={Design and Implementation of Full Adder Cell with the GDI Technique Based on 0 . 18 $\mu$ m CMOS Technology},
  author={Amin Bazzazi and B. Eskafi}

Figures and Tables from this paper


This project presented with 4-bit arithmetic logical unit design with the use of Gate Diffusion Input Technique, a technique of low power digital combinational design that allows less power consumption and reduced propagation delay for low -power design of combinatorial digital circuits with minimum number of transistors.

Design and Implementation of 17 Transistors Full Adder cell

A 17 transistor full adder cell is proposed and Fifteen states of the arts 1-bit full adders are taken for comparison and one proposed fullAdder is simulated with TSPICE using 0.18 micro meter CMOS Technology with the supply voltage of 1.8v.

Full Adder Circuits using Static Cmos Logic Style: A Review

This paper presents 1-bit CMOS full adder cell using standard static CMOS logic style. The comparison is taken out using several parameters like number of transistors, delay, power dissipation and

Design and implementation of low power 1-bit full adder cell using GDI technique

This proposed work illustrates the design of the low-power less transistor full adder designs using cadence tool and virtuoso platform, the entire simulations have been done on 180nm technology, in virtUoso platform of Cadence tool with the supply voltage 1.8V.

Design and Performance Analysis of 1 bit Full Adder in 45nm Technology Using Multiplexer Based GDI Logic

  • Engineering
  • 2016
This paper proposes a new method for implementing a low power full adder by multiplexer based Gate Diffusion Input (GDI) and Pass Transistors using 90nm and 45nm technology. Full adder is a very

A Design of Low Power Low Area High Speed Full Adder Using GDI Technique

GDI is a new method for reducing the power consumption, propagation delay, with less transistor count and power delay product (PDP), and the design has more efficient with less area, less power consumption and high speed as compared to CMOS techniques.

Low Power 10T XOR based 1 Bit Full Adder

The popularity and necessity of portable electronic systems by users have strongly influenced VLSI designers to make great effort for reduced silicon area, improved speeds, long duration battery

Design & study of a low power high speed full adder using GDI multiplexer

The explored technique of realization achieves a low power high speed design for a widely used subcomponent-full adder for VLSI chips.

Design and Implementation of Low-Power High-Speed Full Adder cell using GDI Technique

317 Abstract – Full custom implementation is used to develop digital circuits in new technology to achieve high performance low power and area efficient designs. In this paper, The low power and high

Asynchronous design of energy efficient full adder

In this work, a full adder cell using DPTAAL is designed and simulated, which exhibits less energy and reliable logical operations and double pass transistor logic (DPL) is introduced to improve the circuit performance at reduced voltage level.



A review of 0.18-μm full adder performances for tree structured arithmetic circuits

The proposed hybrid full adder exhibits not only the full swing logic and balanced outputs but also strong output drivability, and remains one of the best contenders for designing large tree structured arithmetic circuits with reduced energy consumption while keeping the increase in area to a minimum.

A high-speed hybrid Full Adder with low power consumption

After determining topology a proposed CAD (Computer Aided Design) with a proposed multi objective genetic algorithm will be used to optimize the high speed hybrid Full Adder with low power consumption.

Performance analysis of low-power 1-bit CMOS full adder cells

A performance analysis of 1-bit full-adder cell is presented, after the adder cell is anatomized into smaller modules, and several designs of each of them are developed, prototyped, simulated and analyzed.

Low-Power and High-Performance 1-Bit CMOS Full-Adder Cell

Simulation results illustrate the superiority of the resulting proposed adder against conventional CMOS 1-bit full-adder in terms of power, delay and PDP.

Two New Low-Power and High-Performance Full Adders

Two new low- power, and high-performance 1-bit Full Adder cells are proposed in this paper, based on low-power XOR/XNOR circuit and Majority-not gate, which produces Cout (Output Carry).

A Novel Low-Power Low-Voltage CMOS 1-Bit Full Adder Cell with the GDI Technique

A novel design of a low power 1-bit full adder cell is proposed, where the GDI technique has been used for the simultaneous generation of XOR and XNOR functions and has the lowest power-delay product over a wide range of voltages among several low-power adder cells of different CMOS logic styles.

A Design of High Speed 1-Bit Full Adder Cell using 0.18 µm Cmos Process

  • Proceeding of The 23 rd International Technical Conference on Circuits/Systems, Computers and communications
  • 2008

Digital Integrated Circuits, A Design

  • Digital Integrated Circuits, A Design
  • 2002