• Corpus ID: 9189472

Design and Implementation of Full Adder Cell with the GDI Technique Based on 0 . 18 μ m CMOS Technology

@inproceedings{BazzaziDesignAI,
  title={Design and Implementation of Full Adder Cell with the GDI Technique Based on 0 . 18 $\mu$ m CMOS Technology},
  author={Amin Bazzazi and B. Eskafi}
}

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References

SHOWING 1-9 OF 9 REFERENCES

A review of 0.18-μm full adder performances for tree structured arithmetic circuits

TLDR
The proposed hybrid full adder exhibits not only the full swing logic and balanced outputs but also strong output drivability, and remains one of the best contenders for designing large tree structured arithmetic circuits with reduced energy consumption while keeping the increase in area to a minimum.

A high-speed hybrid Full Adder with low power consumption

TLDR
After determining topology a proposed CAD (Computer Aided Design) with a proposed multi objective genetic algorithm will be used to optimize the high speed hybrid Full Adder with low power consumption.

Performance analysis of low-power 1-bit CMOS full adder cells

TLDR
A performance analysis of 1-bit full-adder cell is presented, after the adder cell is anatomized into smaller modules, and several designs of each of them are developed, prototyped, simulated and analyzed.

Low-Power and High-Performance 1-Bit CMOS Full-Adder Cell

TLDR
Simulation results illustrate the superiority of the resulting proposed adder against conventional CMOS 1-bit full-adder in terms of power, delay and PDP.

Two New Low-Power and High-Performance Full Adders

TLDR
Two new low- power, and high-performance 1-bit Full Adder cells are proposed in this paper, based on low-power XOR/XNOR circuit and Majority-not gate, which produces Cout (Output Carry).

A Novel Low-Power Low-Voltage CMOS 1-Bit Full Adder Cell with the GDI Technique

TLDR
A novel design of a low power 1-bit full adder cell is proposed, where the GDI technique has been used for the simultaneous generation of XOR and XNOR functions and has the lowest power-delay product over a wide range of voltages among several low-power adder cells of different CMOS logic styles.

A Design of High Speed 1-Bit Full Adder Cell using 0.18 µm Cmos Process

  • Proceeding of The 23 rd International Technical Conference on Circuits/Systems, Computers and communications
  • 2008

Digital Integrated Circuits, A Design

  • Digital Integrated Circuits, A Design
  • 2002