Corpus ID: 15966938

Design and Implementation of Floating Point Multiplier for Better Timing Performance

  title={Design and Implementation of Floating Point Multiplier for Better Timing Performance},
  author={G. Kumar},
IEEE Standard 754 floating point is the most common representation today for real numbers on computers. This paper gives a brief overview of IEEE floating point and its representation. This paper describes a single precision floating point multiplier for better timing performance. The main object of this paper is to reduce the power consumption and to increase the speed of execution by implementing certain algorithm for multiplying two floating point numbers. In order to design this VHDL is the… Expand
5 Citations


Implementation of IEEE single precision floating point addition and multiplication on FPGAs
A re-evaluation of the practicality of floating-point operations on FPGAs
Quantitative analysis of floating point arithmetic on FPGA based custom computing machines
Pebble: A Language for Parametrised and Reconfigurable Hardware Design
Customising graphics applications: techniques and programming interface
  • H. Styles, W. Luk
  • Computer Science
  • Proceedings 2000 IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00871)
  • 2000
Digit-Serial Computation
An architecture for electrically configurable gate arrays
Computer Organization and Architecture
  • M. Flynn
  • Computer Science
  • Advanced Course: Operating Systems
  • 1978