Corpus ID: 212600350

Design and Implementation of Fast Locking and Harmonic Free in Multiphase Digital DLL – Robust to Process Variations

@inproceedings{Karthik2013DesignAI,
  title={Design and Implementation of Fast Locking and Harmonic Free in Multiphase Digital DLL – Robust to Process Variations},
  author={T. Karthik and V. Senthilkumar},
  year={2013}
}
An ADMDLL(All Digital Multiphase Delay Locked Loop) with Harmonic free , Low power , Low Jitter and Immune to SSN features are presented. Harmonic Free and Immune to SSN of the proposed ADMDLL are achieved by implementing a Narrow-Wide Coarse Lock Detector (NWCLD) and Time to Digital Converter (TDC),which maintains the delay between reference clock and outgoing clock with in the suitable range along with the main Phase Frequency Detector (PFD) and also it monitors the coarse locking range… Expand

References

SHOWING 1-9 OF 9 REFERENCES
An Ultra-Low Power Harmonic-Free Multiphase DLL Using a Frequency-Estimation Selector
This paper presents an all-digital multiphase delay-locked loop (ADMDLL) for wide-locking range and micro-power applications. To enhance locking range and locking speed of the ADMDLL, we proposed theExpand
A Wide-Range Multiphase Delay-Locked Loop Using Mixed-Mode VCDLs
TLDR
A wide-range multiphase delay-locked loop (DLL) using an analog 3-states phase-frequencydetector (PFD) and the proposed digital PFD can achieve low jitter oper-ation over a wide frequency range without harmonic locking problems. Expand
A 40–550 MHz Harmonic-Free All-Digital Delay-Locked Loop Using a Variable SAR Algorithm
TLDR
The variable successive approximation register-controlled algorithm is proposed to eliminate the harmonic-locking issue in wide-range operation and achieve the fast-locking property and closed-loop operation. Expand
Process variation tolerant all-digital multiphase DLL for DDR3 interface
TLDR
The measured large locking delay code difference between four 90° phase shift delay lines in the proposed DLL implemented in 45nm CMOS process, which corresponds to ±31ps at 800MHz, proves that the DLL corrects significant phase error caused by delay mismatch. Expand
Clock aligner based on delay locked loop with double edge synchronization
TLDR
Results of its SPICE simulation, that relate to 1.2 μm CMOS technology, have shown that the duty-cycle of the multistage output pulses can be precisely adjusted to (50 ± 1)% within the operating frequency range, from 55 MHz up to 166 MHz. Expand
A new DLL-based approach for all-digital multiphase clock generation
A new DLL-based approach for all-digital multiphase clock generation is presented. By using the time-to-digital converter (TDC) with fixed-step search scheme, the proposed all-digital and cell-basedExpand
An All-Digital 90-Degree Phase-Shift DLL with Loop-Embedded DCC for 1.6Gbps DDR Interface
An all-digital 90deg phase-shift DLL is proposed for 1.6 Gbps DDR interface by using a loop-embedded DCC and a binary phase detector with the lock range extended to 0~4pi radians. The DCC has a smallExpand
Device mismatch and tradeoffs in the design of analog circuits
  • P. Kinget
  • Engineering
  • IEEE Journal of Solid-State Circuits
  • 2005
Random device mismatch plays an important role in the design of accurate analog circuits. Models for the matching of MOS and bipolar devices from open literature show that matching improves withExpand
An Ultra - Low Power HarmonicFree Multiphase DLL Usinga FrequencyEstimation Selector ” , 20 th VLSI Design / CAD Symposium
  • 2009