Corpus ID: 17298878

Design and Implementation of FFT Processor Using Vedic Multiplier With High Throughput

@inproceedings{Agarwal2013DesignAI,
  title={Design and Implementation of FFT Processor Using Vedic Multiplier With High Throughput},
  author={Jyoti Agarwal and Vijay Matta and Dwejendra Arya},
  year={2013}
}
In present scenario every process should be rapid, efficient and simple. Fast Fourier transform (FFT) is an efficient algorithm to compute the N point DFT. It has great applications in communication, signal and image processing and instrumentation. But the Implementation of FFT requires large number of complex multiplications, so to make this process rapid and simple it's necessary for a multiplier to be fast and power efficient. To tackle this problem Urthva Tirvagbhyam in Vedic mathematics is… Expand
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