Design and Implementation of BISR for 3 d Multiple SRAMS with Redundancies in a SOC


Embedded memories contain several hundreds of memory cores which constitute a significant portion of the chip area for typical system-on-chip (SOC) designs. With the shrinking transistor size and aggressive design rules, memory cores are easily prone to manufacturing defects and reliability problems. As these circuits have higher complexity and more sharing signals than logic blocks, they have higher failure possibilities In order to solve this problem; designers usually add redundancy to embedded memories. Most of faults are single cell transient fault; the area of spare is effectively utilized by replacing defected cell with spare cell. Continuing advancements in semiconductor technology have made sure that the integrated circuit industry keeps following the Moore’s law, which predicts doubling the circuit density at a constant rate. This has been possible due to continuous scaling of CMOS transistor size and innovations in packaging. BISR is actually known and available for regular structures such as memory blocks, but is little difficult to implement on irregular logic. So the repairable memories play a vital role in improving the yield of chip.In this paper we present the efficient Reconfigurable Built-in Self Repair (Re BISR) circuit which increases repair rate. The proposed repair circuit is Reconfigurable for less area, used to repair multiple memories with different in size and redundancy. Built-in self-repair (BISR) techniques are widely used for enhancing the yield of embedded memories The techniques used for yield improvements in memories are Built In Self Test (BIST) and BIRA.BIST will verify the memory location by using MARCH CW algorithm .BIRA will perform built-in redundancy-analysis using BIRA algorithm for redundancy allocation A shared parallel BISR can test and repair multiple RAMs simultaneously. Typically, many RAMs with various sizes are included in an SOC. Memory designers usually employ efficient built-in redundancy-analysis (BIRA) algorithms which can costeffectively be realized with built-in circuitries that are required for BISR schemes. Which are done by using spare rows and/or spare columns and spare I/O

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@inproceedings{Latha2013DesignAI, title={Design and Implementation of BISR for 3 d Multiple SRAMS with Redundancies in a SOC}, author={C . V . Keerthi Latha and R. Latha}, year={2013} }