Computer simulations of a 20 Gigasample/second, 500 MHz eight-bit, analog-todigital converter
- G. T. Mailick
- IEEE Trans. Magn.,
-A design of a comparator for an all HTC superconductive 4-bit flash A/D converter is proposed and discussed. The design has been simulated and optimized using the PSCAN computer package [1,2]. The required junction and circuit parameters are thus calculated and compared with the experimental junction parameters. The operating temperature is intended to be as high as 40 K. Due to the current noise-level at these temperatures the I, of the junctions should be higher than 100 pA. The output voltages should be of the order of 500 pV and higher. The junctions in the quasi-one junction SQUID are structured on 2 ramp-edges. The operating frequencies will be below 1 MHz in this first design. Optimization to the GHz range seems very well possible. A first realization uses the YBa$u,O,, (YBCO) superconductor and PrBa&u,O,, (PBCO) as junction barrier and electrode inter layer material. On a 10x10 mm2 SrTiO, (001) substrate, 9 comparators and 4 separate ramp-edge junctions are realized. This relative large number of elements on a wafer should allow us to extract statistical information on the scattering of properties due to the fabrication processes.