Design and DfT of a High-Speed Area-Efficient Embedded Asynchronous FIFO

@article{Wielage2007DesignAD,
  title={Design and DfT of a High-Speed Area-Efficient Embedded Asynchronous FIFO},
  author={Paul Wielage and Erik Jan Marinissen and Michel Altheimer and Clemens Wouters},
  journal={2007 Design, Automation & Test in Europe Conference & Exhibition},
  year={2007},
  pages={1-6}
}
Embedded First-In First-Out (FIFO) memories are increasingly used in many IC designs. We have created a new full-custom embedded ripple-through FIFO module with asynchronous read and write clocks. The implementation is based on a micropipeline architecture and is at least a factor two smaller than SRAM-based and standard-cell-based counterparts. This paper gives an overview of the most important design features of the new FIFO module and describes its test and design-for-test approach. 
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