• Corpus ID: 7536870

Design and Calibration of a 12-Bit Current-Steering DAC Using Data-Interleaving

  title={Design and Calibration of a 12-Bit Current-Steering DAC Using Data-Interleaving},
  author={Benjamin Jankunas},
i ABSTRACT High speed current-steering DACs with high linearity are needed in today's applications such as wired and wireless communications, instrumentation, radar, and other direct digital synthesis (DDS) applications. However, a trade-off exists between the speed and resolution of Nyquist rate current-steering DACs. As the resolution increases, more transistor area is required to meet matching requirements for optimal linearity and thus, the overall speed of the DAC is limited. In this… 

Machine Learning Based Image Calibration for a Twofold Time-Interleaved High Speed DAC

  • D. BeauchampK. Chugg
  • Computer Science
    2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)
  • 2019
A novel image calibration algorithm for a twofold time-interleaved DAC (TIDAC) based on simulated annealing, which is often used in the field of machine learning to solve derivative-free optimization (DFO) problems.



A 14-bit 200-MHz Current-Steering DAC With Switching-Sequence Post-Adjustment Calibration

In this paper, a novel calibration method for high-accuracy current-steering DACs is presented. Different from traditional calibration methods which achieves the calibration by adjusting the current

A 14b , 100-MS / s CMOS DAC Designed for Spectral Performance

A 14-bit, 100-MS/s CMOS digital-to-analog converter (DAC) designed for spectral performance corresponding more closely to the 14-bit specification than current implementations is presented. This DAC

A Low Cost Calibrated DAC for High-Resolution Video Display System

This paper presents a digitally enhanced strategy for current-steering digital-to-analog converters (DACs) applied to video systems and demonstrates that the calibrated converter achieves fully 12-bit linearity with both DNL and INL less than 0.5 LSB.

Modeling of CMOS digital-to-analog converters for telecommunication

This paper gives an overview of some of the effects caused by circuit mismatch and parasitics in binary weighted digital-to-analog converters (DACs), and, as a special case, a current-steering CMOS

A 1.6-GS/s 12-bit return-to-zero GaAs RF DAC for multiple Nyquist operation

Return-to-zero (RZ) current switches are added to current steering DAC for high-frequency wideband applications to achieve 800-MHz bandwidth at first and second Nyquist band without the need for a reverse sinc equalization filter in wideband transmitter application.

DDL-based calibration techniques for timing errors in current-steering DACs

Two digital-delay-line (DDL) based calibration techniques for timing errors are demonstrated and Matlab behavior level simulation results show that these two on-chip calibration techniques can improve the SFDR performance.

Current switch driver and current source designs for high-speed current-steering DAC

A high output impedance current source circuit is presented, and a gain stage is utilized in the biasing circuit of the current source, and the output impedance of the proposed current reaches 108 Omega, which is important to fulfill the performance requirements of the DAC.

A 14 bit 200 MS/s DAC With SFDR >78 dBc, IM3 < -83 dBc and NSD <-163 dBm/Hz Across the Whole Nyquist Band Enabled by Dynamic-Mismatch Mapping

By optimizing the switching sequence of current cells to reduce the dynamic integral nonlinearity in an I-Q domain, the DMM technique digitally calibrates all mismatch errors so that both the DAC static and dynamic performance can be significantly improved in a wide frequency range.

Output impedance requirements for DACs

  • S. LuschasHae-Seung Lee
  • Computer Science
    Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03.
  • 2003
It is shown that the output impedance required in a fully-differential implementation of a DAC is much lower than that needed in a single-ended one, allowing DACs to scale with technology to reduced supply voltages.

A 1.5 V 14 b 100 MS/s self-calibrated DAC

  • Yonghua CongR. Geiger
  • Engineering
    2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.
  • 2003
A calibrated 14 b current-steering DAC is fabricated in a 0.13 /spl mu/m digital CMOS process. The DAC achieves 14 b static linearity with a single 1.5 V supply, and the core occupies 0.1 mm/sup 2/.