Design and CAD methodologies for low power gate-level monolithic 3D ICs

@article{Panth2014DesignAC,
  title={Design and CAD methodologies for low power gate-level monolithic 3D ICs},
  author={Shreepad Panth and Kambiz Samadi and Yang Du and Sung Kyu Lim},
  journal={2014 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)},
  year={2014},
  pages={171-176}
}
In a gate-level monolithic 3D IC (M3D), all the transistors in a single logic gate occupy the same tier, and gates in different tiers are connected using nano-scale monolithic inter-tier vias. This design style has the benefit of the superior power-performance quality offered by flat implementations (unlike block-level M3D), and zero total silicon area overhead compared to 2D (unlike transistor-level M3D). In this paper we develop, for the first time, a complete RTL-to-GDSII design flow for… CONTINUE READING
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