Design and Analysis of a Self-Repairing SRAM with On-Chip Monitor and Compensation Circuitry


In an SRAM array, the systematic inter-die and the random within-die variations in process parameters cause significant number of parametric failures, to degrade process yield in the nanometer technology regime. In this paper, we investigate the interaction between the inter-die and intra-die Vt variations on SRAM read and write failures. To improve… (More)
DOI: 10.1109/VTS.2008.26


11 Figures and Tables