Corpus ID: 201131870

Design and Analysis of Low power,High Speed PLL Frequency Synthesizer using Dynamic CMOS VLSI Technology

@article{Hannah2019DesignAA,
  title={Design and Analysis of Low power,High Speed PLL Frequency Synthesizer using Dynamic CMOS VLSI Technology},
  author={D.Sharon Hannah and Yedla Nikitha},
  journal={Journal of emerging technologies and innovative research},
  year={2019}
}
Power and speed are the important parameters in various communication systems. Phase locked loop (PLL) is an efficient method used in frequency synthesis. A dynamic logic based CMOS is proposed to design phase detector, VCO and loop filter. The CMOS dynamic logic is the fastest logic in all the CMOS logic families. The DSCH3 tool is used in the design of logical circuits and microwind2 tool using 90nm CMOS technology is used to measure the parametric analysis. The speed of transition time… Expand

References

SHOWING 1-9 OF 9 REFERENCES
Design of low power, high speed PLL frequency synthesizer using dynamic CMOS VLSI technology
TLDR
A dynamic logic based CMOS is proposed to design phase detector, VCO and loop filter to handle the power consumption and the speed of transition time between the synthesized frequencies gives the bandwidth of loop filter. Expand
LOW POWER AND LOW JITTER PHASE FREQUENCY DETECTOR FOR PHASE LOCK LOOP
This paper presents three types of phase frequency detectors – traditional PFD, modified PFD and high speed PFD. With the comparison of Low power and low jitter phase frequency detector the highExpand
Study of VLSI Implementation of Fractional-N PLL using 32nm and 45nm Technology “,International
  • Journal of Engineering Research and General Science”
  • 2015
Design of low power Phase Locked Loop in submicron techno logy",IJATER
  • Proceedings of ISSN NO.22503536
  • 2012
Low Power and Low Jitter Phase Frequency Detector for Phase Lock Loop" International Journal of Engineering Science and Technology (IJEST),Volume: 3,2011
  • 2011
Thakore " Low Power and Low Jitter Phase Frequency Detector for Phase Lock Loop
  • International Journal of Engineering Science and Technology ( IJEST )
  • 2011
Design of Low Power PLL using 45NM VLSI Technology
    Design of low power Phase Locked Loop in submicron techno logy
    • IJATER Proceedings of ISSN
    Study of VLSI Implementation of Fractional-N PLL using 32nm and 45nm Technology
    • International Journal of Engineering Research and General Science