• Corpus ID: 50506910

Design and Analysis of Low Power and High Speed Dynamic Latch Comparator in 0 . 18 μ m CMOS Process

@inproceedings{MohdDesignAA,
  title={Design and Analysis of Low Power and High Speed Dynamic Latch Comparator in 0 . 18 $\mu$ m CMOS Process},
  author={Raja Mohd and N. Daud and Mamun Bin Ibne Reaz and Labonnah Farzana Rahman}
}
amplifier stage is presented. The designed dynamic latch comparator is required for high-speed analog-to-digital converters to get faster signal conversion and to reduce the power dissipation, which is immune to noise than the previous works. In this paper, the design and analysis of a latch comparator using charge sharing circuit topology is illustrated to achieve low power and high-speed operation. The proposed circuit is designed using 0.18µm CMOS process. The simulated results shows that… 

Figures and Tables from this paper

Design of Low Power & High Speed Comparator with 0.18µm Technology for ADC Application

In Analog to Digital Converter (ADC), high speed comparator influences the overall performance of ADC directly. This paper presents the high speed & low power design of a CMOS comparator. Schematic

Design of Low Power Area Efficient Double Tail Comparator

Comparator is fundamental building blocks in analog-todigital converters. CMOS comparator which has dual input, dual output inverter stage suitable for high speed analog-to-digital such as flash

High Speed Low Power CMOS Comparator using Forward Body Bias Technique in 0.13 µm Technology

TLDR
This paper presents the design of high speed and low power CMOS comparator using a forward body bias technique in 0.13-µm technology and has significantly reduced both the power and delay time compared to the previous design.

Low Power and High Speed CMOS Comparator for A/D Converter Applications - A Review

TLDR
A basic SA-ADC (successive approximation) is discussed as a proper choice for low power applications and comparison with other ADC architectures following with the study of design parameters of comparator, their architectures and its use in various applications.

Analysis and Design of a New Modified Double-Tail Comparator for High Speed ADC Applications: A Review

TLDR
This paper provides a comprehensive review about a variety of comparator designs - in terms of performance, power and delay using Cadence Virtuoso CMOS 180-nm technology.

A low-offset low-power and high-speed dynamic latch comparator with a preamplifier-enhanced stage

Department of Physics, Laboratory of Energy, Electrical and Electronics Systems, University of Yaoundé I, Yaoundé, Cameroon Multidisciplinary Laboratory (MLAB), International Centre for Theoretical

IJSRD-International Journal for Scientific Research & Development| Vol. 4, Issue 04, 2016 | ISSN (online): 2321-0613

Dispersion compensation is the essential feature of an optical transmission system. Two widely used dispersion compensation techniques i.e. Fiber Bragg Grating (FBG) and Dispersion Compensation Fiber

References

SHOWING 1-9 OF 9 REFERENCES

A Comparator With Reduced Delay Time in 65-nm CMOS for Supply Voltages Down to 0.65 V

A comparator in a low-power 65-nm complementary metal-oxide-semiconductor process (only standard transistors with threshold voltage Vt ap 0.4 V were used) is presented, where the circuit of a

A low-noise self-calibrating dynamic comparator for high-speed ADCs

This paper presents a low offset voltage, low noise dynamic latched comparator using a self-calibrating technique. The new calibration technique does not require any amplifiers for the offset voltage

A low-offset latched comparator using zero-static power dynamic offset cancellation technique

A low-offset latched comparator using new dynamic offset cancellation technique is proposed. The new technique achieves low offset voltage without pre-amplifier and quiescent current. Furthermore the

Low-power and low-offset comparator using latch load

TLDR
A low-power and low-offset latched comparator using dynamic offset cancellation and a latch load is proposed, which reduces the power consumption and offset voltage of the comparator.

A Novel 1GSPS Low Offset Comparator for High Speed ADC

International Journal of Information and Electronics Engineering

  • International Journal of Information and Electronics Engineering
  • 2012

Design of a CMOS Comparator for Low Power and High Speed

  • Proc . IEEE Asian Solid State Circuit Conference ( A - SSCC )

Low Power and High Speed CMOS Comparator Design Using 0.18µm Technology

  • International Journal of Electronic Engineering Research
  • 2010

Design of a CMOS Comparator for Low Power and High Speed

  • International Journal of Electronic Engineering Research
  • 2010