Corpus ID: 50506910

Design and Analysis of Low Power and High Speed Dynamic Latch Comparator in 0 . 18 μ m CMOS Process

@inproceedings{MohdDesignAA,
  title={Design and Analysis of Low Power and High Speed Dynamic Latch Comparator in 0 . 18 μ m CMOS Process},
  author={Raja Mohd and Noor Hafizi Raja Daud and M. Reaz and L. F. Rahman}
}
amplifier stage is presented. The designed dynamic latch comparator is required for high-speed analog-to-digital converters to get faster signal conversion and to reduce the power dissipation, which is immune to noise than the previous works. In this paper, the design and analysis of a latch comparator using charge sharing circuit topology is illustrated to achieve low power and high-speed operation. The proposed circuit is designed using 0.18µm CMOS process. The simulated results shows that… CONTINUE READING
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Design of a CMOS Comparator for Low Power and High Speed
  • Proc . IEEE Asian Solid State Circuit Conference ( A - SSCC )