Design and Analysis of Even-Sized Binary Shuffle-Exchange Networks for Multiprocessors

@article{Padmanabhan1991DesignAA,
  title={Design and Analysis of Even-Sized Binary Shuffle-Exchange Networks for Multiprocessors},
  author={Krishnan Padmanabhan},
  journal={IEEE Trans. Parallel Distrib. Syst.},
  year={1991},
  volume={2},
  pages={385-397}
}
The architecture and performance of binary shuffle-exchange networks of any size are investigated. It is established that a network with a shuffle-exchange stages whose number equals the least integer >or=log/sub 2/N or a single recirculating stage can provide the connectivity between N inputs and N outputs using a distributed tag-based control algorithm. Control tags depend on both source and destination when N is not a power of two and can be computed in a simple manner. Several structural… CONTINUE READING

Topics from this paper.

Citations

Publications citing this paper.
SHOWING 1-10 OF 13 CITATIONS

On Shortest Path Routing in Single Stage Shuffle-Exchange Networks

VIEW 7 EXCERPTS
CITES BACKGROUND & METHODS
HIGHLY INFLUENCED

A novel high-performance and low-power mesh-based NoC

  • 2008 IEEE International Symposium on Parallel and Distributed Processing
  • 2008
VIEW 1 EXCERPT
CITES BACKGROUND

Highly scalable interconnection network for parallel image processing

  • International Symposium on Multispectral Image Processing and Pattern Recognition
  • 2001