Design and Analysis of A 5.3-pJ 64-kb Gated Ground SRAM With Multiword ECC

@article{Jahinuzzaman2009DesignAA,
  title={Design and Analysis of A 5.3-pJ 64-kb Gated Ground SRAM With Multiword ECC},
  author={S. Jahinuzzaman and J. Shah and D. J. Rennie and Manoj Sachdev},
  journal={IEEE Journal of Solid-State Circuits},
  year={2009},
  volume={44},
  pages={2543-2553}
}
This paper presents an SRAM architecture employing a multiword-based ECC (MECC) scheme for soft error mitigation and a row virtual ground technique for array leakage reduction. The MECC combines four data words to form a 128 bit composite ECC word, two of which are interleaved in a row to mitigate cosmic neutron-induced multi-bit errors. The use of a composite word reduces the number of check-bits by 68%, however, requires a unique write operation that updates the check-bits by writing one data… CONTINUE READING
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