Design and Analysis of 3D-MAPS (3D Massively Parallel Processor with Stacked Memory)

@article{Kim2015DesignAA,
  title={Design and Analysis of 3D-MAPS (3D Massively Parallel Processor with Stacked Memory)},
  author={Daehyun Kim and Krit Athikulwongse and Michael B. Healy and Mohammad M. Hossain and Moongon Jung and Ilya Khorosh and Gokul Kumar and Young-Joon Lee and Dean L. Lewis and Tzu-Wei Lin and Chang Liu and Shreepad Panth and Mohit Pathak and Minzhen Ren and Guanhao Shen and Taigon Song and Dong Hyuk Woo and Xin Zhao and Joungho Kim and Ho Choi and Gabriel H. Loh and Hsien-Hsin S. Lee and Sung Kyu Lim},
  journal={IEEE Transactions on Computers},
  year={2015},
  volume={64},
  pages={112-125}
}
This paper describes the architecture, design, analysis, and simulation and measurement results of the 3D-MAPS (3D massively parallel processor with stacked memory) chip built with a 1.5 V, 130 nm process technology and a two-tier 3D stacking technology using 1.2 \microm-diameter, 6 \micro m-height through-silicon vias (TSVs) and 3.4\nbsp\microm-diameter face-to-face bond pads. 3D-MAPS consists of a core tier containing 64 cores and a memory tier containing 64 memory blocks. Each core… CONTINUE READING