Design Trade-offs of a 6 T FinFET SRAM Cell in the Presence of Variations
@inproceedings{Chin2007DesignTO, title={Design Trade-offs of a 6 T FinFET SRAM Cell in the Presence of Variations}, author={Eric B. Chin and M. Dunga and B. Nikoli{\'c}}, year={2007} }
As the impact of process variations become increasingly significant in ultra deep submicron technologies, FinFETs are becoming increasingly popular a contender for replacement of bulk FETs due to favorable device characteristics. This paper explores the impacts of random and systematic process variations on SRAM cell stability and timing. The largest contributors to these robustness and timing metrics are identified. Design tradeoffs are explored in optimizing the SRAM cell for increased… CONTINUE READING
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References
SHOWING 1-8 OF 8 REFERENCES
FinFET-based SRAM design
- Engineering, Medicine
- ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005.
- 2005
- 157
- PDF
Modeling and estimation of failure probability due to parameter variations in nano-scale SRAMs for yield enhancement
- Engineering
- 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525)
- 2004
- 91
- PDF
Fluctuation limits & scaling opportunities for CMOS SRAM cells
- Physics
- IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.
- 2005
- 185
- PDF
Technology and circuit design considerations in quasi-planar double-gate SRAM
- Physics
- IEEE Transactions on Electron Devices
- 2006
- 29
Dependability analysis of nano-scale FinFET circuits
- Computer Science
- IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06)
- 2006
- 47
- PDF
Design Optimization of Ultra-Scaled Transistors and the Impact of Process Variations
- EECS Department, Technical Report UCB/ERL M04/48, UC Berkeley, 2004.
- 2004