• Corpus ID: 18895375

Design Trade-offs of a 6 T FinFET SRAM Cell in the Presence of Variations

@inproceedings{Chin2007DesignTO,
  title={Design Trade-offs of a 6 T FinFET SRAM Cell in the Presence of Variations},
  author={Eric Y. Chin and Mohan V. Dunga and Borivoje Nikoli{\'c}},
  year={2007}
}
As the impact of process variations become increasingly significant in ultra deep submicron technologies, FinFETs are becoming increasingly popular a contender for replacement of bulk FETs due to favorable device characteristics. This paper explores the impacts of random and systematic process variations on SRAM cell stability and timing. The largest contributors to these robustness and timing metrics are identified. Design tradeoffs are explored in optimizing the SRAM cell for increased… 

Figures and Tables from this paper

20nm FinFET-based SRAM cell: Impact of variability and design choices on performance characteristics

  • S. KarapetyanUlf Schlichtmann
  • Engineering
    2017 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)
  • 2017
TLDR
Design choices for 20nm FinFET-based SRAM cells are explored and the impact of process variations on the performance characteristics of the SRAM cell is analyzed.

Comparative Study of 8 T SRAM Cell using CMOS , FinFET and CNTFET in Nanoscale Technologies

In the world of Integrated Circuits, Complementary Metal–Oxide– Semiconductor (CMOS) has lost its credentiality during scaling beyond 32nm. Scaling causes severe Short Channel Effects (SCE) which are

Analysis of Leakage Reduction Techniques in Independent-Gate DG FinFET SRAM Cell

TLDR
Independent-gate FinFET SRAM cell using various leakage reduction techniques has been simulated using Cadence virtuoso tool in 45 nm technology and power consumption in theSRAM cell is reduced and provides better performance.

Nanoscale FinFET Based SRAM Cell Design: Analysis of Performance Metric, Process Variation, Underlapped FinFET, and Temperature Effect

In this paper the analysis of SNM, RNM, WNM and static power variation with width of access, load and driver have been carried out for nanoscale FinFET based SRAM cell. FinFET based SRAM design has

A Study Of Three-Dimensional FinFET Source / Drain Structure

FinFETs have emerged as alternatives to conventional bulk MOSFETs in scaled technologies due to better gate control of the channel, lower short channel effects and higher scalability. However, width

Performance Analysis of FinFET based SRAM at Nano-scaled Technology Nodes

TLDR
The focus of the paper is to study 6T FinFET SRAM, and evaluate the different performance metrics such as delay, power dissipation and PDP at deep-submicron technology nodes.

Ultra-low-leakage, Robust FinFET SRAM Design Using Multiparameter Asymmetric FinFETs

TLDR
This article shows how Multiparameter Asymmetric (MPA) FinFETs can be used to design ultra-low-leakage and robust 6T SRAM cells and combines multiple asymmetries, namely, asymmetry in gate work function, source/drain doping concentration, and gate underlap, to address various SRAM design issues all at once.

Design and Performance Comparison of 6-T SRAM Cell in 32nm CMOS, FinFET and CNTFET Technologies

TLDR
The objective of this work mainly focus on designing 6-T SRAM cell in 32nm CMOS, CNTFET as well as FinFET and finally, to compare the parameters such as average power, delay and leakage current.

Analysis and design of low power SRAM cell using independent gate FinFET

TLDR
A six transistor SRAM cell based on independent-gate FinFET technology is described in this paper for simultaneously reducing the active and standby mode power consumption.

Performance Improvement of FinFET using Nitride Spacer

The Double Gate FinFET has been designed for 90nm as an alternative solution to bulk devices. The FinFET with independent gate (IDG) structure is designed to control Vth. When the Vth is controlled

References

SHOWING 1-8 OF 8 REFERENCES

The impact of intrinsic device fluctuations on CMOS SRAM cell stability

Reductions in CMOS SRAM cell static noise margin (SNM) due to intrinsic threshold voltage fluctuations in uniformly doped minimum-geometry cell MOSFETs are investigated for the first time using

Modeling and estimation of failure probability due to parameter variations in nano-scale SRAMs for yield enhancement

In this paper we have analyzed and modeled the failure probabilities (access time failure, read/write stability failure, and hold stability failure in the stand-by mode) of SRAM cells due to process

Fluctuation limits & scaling opportunities for CMOS SRAM cells

Fundamental limitations on scaling CMOS SRAM cell transistor dimensions and operating voltages are demonstrated by measuring the local stochastic distributions of read, write and retention DC margins

Static-noise margin analysis of MOS SRAM cells

The stability of both resistor-load (R-load) and full-CMOS SRAM cells is investigated analytically as well as by simulation. Explicit analytic expressions for the static-noise margin (SNM) as a

Technology and circuit design considerations in quasi-planar double-gate SRAM

TLDR
This paper explores both approaches to selecting the right combination of device structure, V/sub t/ and V/ sub dd/ that achieves maximum stability and minimum leakage over the design space, and explores the impact of FinFET design choices on device and SRAM circuit metrics.

Dependability analysis of nano-scale FinFET circuits

TLDR
It is concluded that FinFET-based circuit design is more robust than the bulk CMOS based circuit design, which is indicated by better soft error immunity and less impact of process variation.

FinFET-based SRAM design

TLDR
It is found that 6-T and 4-T FinFET-based SRAM cells designed with built-in feedback achieve significant improvements in the cell static noise margin (SNM) without area penalty.

Design Optimization of Ultra-Scaled Transistors and the Impact of Process Variations

  • EECS Department
  • 2004