Design Methodology of Fault-Tolerant Custom 3D Network-on-Chip

@article{Li2017DesignMO,
  title={Design Methodology of Fault-Tolerant Custom 3D Network-on-Chip},
  author={Katherine Shu-Min Li and Sying-Jyan Wang},
  journal={ACM Trans. Design Autom. Electr. Syst.},
  year={2017},
  volume={22},
  pages={63:1-63:20}
}
A systematic design methodology is presented for custom Network-on-Chip (NoC) in three-dimensional integrated circuits (3D-ICs). In addition, fault tolerance is supported in the NoC if extra links are included in the NoC topology. In the proposed method, processors and the communication architecture are synthesized simultaneously in the 3D floorplanning process. 3D-IC technology enables ICs to be implemented in smaller size with higher performance; on the flip side, 3D-ICs suffer yield loss due… CONTINUE READING

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