Design Low Power Adiabatic 5-input OR Gate

Abstract

A novel low power and Positive Feedback Adiabatic Logic (PFAL) 5-input OR Gate is presented in this paper. The power consumption and general characteristics of the PFAL 5 input OR gate are then compared against two low power 5-input OR Gate; Efficient Charge Recovery Logic (ECRL), Conventional CMOS 5-input OR Gate. The proposed PFAL 5-input OR Gate design was proven to be superior to the other two designs in power dissipation and area. The combination of low power and low transistor count makes the new PFAL cell a viable option for low power design.

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Cite this paper

@inproceedings{Madhu2014DesignLP, title={Design Low Power Adiabatic 5-input OR Gate}, author={G. Madhu}, year={2014} }