Design Issues for the Asymmetric Serial Link Measurement Setup and Results a 2gb/s/pin Cmos Asymmetric Serial Link*


The design of an asymmetric serial link poses a number of tradeoffs for the designer. This paper describes measurements from a 0.25μm CMOS test chip which show that a properly designed asymmetric link can achieve 2Gb/s using single-ended signalling with a bit-error rate < 10-14. Architecture Using high-speed serial links in network switches can provide significant performance improvements [1]. However, conventional serial links create hot-spots in large scale switches. For example, employing a conventional serial link at each input of a crossbar chip overly increases its power dissipation due to the 32 PLLs required. As shown in Figure 1, asymmetric links can reduce the power consumed in the crossbar chips, by adjusting the timing of the crossbar inbound links at the transmitters located at the peripheral chips, [2]. Figure 2 shows the block diagram of the asymmetric serial link. The smart end of the link adjusts the phase of both its transmitter and receiver clocks, while the dumb end keeps the phase of both its clocks constant. The timing information, required by the smart end to adjust its transmitter clock, is periodically sent over the dumb-to-smart link. Design Issues for the Asymmetric Serial Link To help understand the capabilities of these links, we built a testchip using Texas Instruments’ 0.25μm CMOS technology. The chip has a single PLL, and a transmitter-receiver pair that can be configured as either the smart or dumb end of an asymmetric link. The four digitallycontrolled precision phase adjusters in the PLL allow us to measure the timing and voltage margins of the system during operation. The test chip helped us answer the following questions: (1) Asymmetric links require explicit calibration of the smart-to-dumb link, so the designer needs to trade-off effective link bandwidth against phase adjust bandwidth. What calibration frequency is required for good timing margins? (2) Since the link cannot transfer data during calibration, the same data receiver could be used to acquire the timing information. Does using the same receiver improve timing margins, and by how much? (3) What is the minimum necessary signal amplitude? Can a singleended link achieve the same performance as a differential link? Implementation The asymmetric link transmits data on both edges of its internal clock, and uses a pair of data receivers to recover alternate data bits. A separate pair of timing receivers is employed at each input to recover timing information, as shown in Figure 3. Noise-tolerant, integrating receivers [5] are used to filter out high-frequency amplitude noise, especially reference voltage noise in the single-ended link. The smart end adjusts both its receiver and transmitter clocks, so that the receivers at both ends of the link integrate the incoming data for the entire bit time. The timing receiver clock (RTClk) is shifted by bit time (90o) from the data receiver clock (RClk), to integrate around the data transition to recover timing information. The clock generation circuitry at the smart end of the links (Figure 4) includes a dual-loop PLL with digitally-controlled phase adjusters [4]. The dashed line encloses the core loop which comprises a VCO-based third-order PLL with a 250MHz reference clock input. The 1GHz VCO clock is digitally divided by four to generate a 250MHz clock, which is phase locked to the reference clock. The six* Supported by Texas Instruments stage VCO uses differential elements with replica-biased symmetric loads [3] to generate twelve clock phases, spaced by 30o. Two adjacent phases are selected by clock multiplexors, which form the first stage of the phase adjusters. A digitally-controlled interpolator mixes the two adjacent phases to generate one of 16 finer phases. As a result, each VCO clock cycle can be subdivided into = 192 phases, which results in a phase resolution of 5 ps for a 1GHz clock. The timing information from each link is processed by a logic block which controls the phase adjusters and in this way closes the outer loop of the dual-loop PLL. Four phase adjusters respectively generate the digital divider clock, the transmitter clock (TClk), the data receiver clock (RClk) and the timing receiver clock (RTClk). However, in normal operation only the transmitter clock phase and the receiver clock phase are adjusted independently. The phase setting for the digital divider clock is fixed, while the phase setting for the timing receiver clock is offset by bit time (90o) relative to the data receiver clock. The phase setting for the dumb-to-smart link can be adjusted continuously while the smart-to-dumb link can only be adjusted periodically. The smart transmitter clock is adjusted based on a majority vote of several bit times of dumb receiver timing information to filter out high-frequency noise. Furthermore, to minimize dither jitter, the phase adjust logic moves the clocks only after the results of its last decision have propagated through the outer loop. The clock generation circuit is carefully tuned so that all the output clock paths have approximately the same delay. As shown in Figure 4, both the receiver clock paths have an extra delay circuit to match the clock-to-output delay of the digital divider in the PLL. The digital divider is sized so that its clock-to-output delay matches that of the transmitter, so no extra delay circuit is needed in the transmitter clock path. As a result, the core PLL loop continuously tracks temperature and supply-induced delay variations within its loop bandwidth. Therefore, the transmitter output and the receiver sample time are kept locked in a fixed relationship to the reference clock. Measurement Setup and Results To measure the timing margins at the receiver output accurately, the user can externally control the phase of each of the internal clocks. For example, one can externally control the phase error between the data receiver clock and the timing receiver clock while the link is in lock until bit errors are detected. Two test chips were used to measure performance, one configured as the dumb end, and the other as the smart end of the link. Figure 5 shows the 2Gb/s measured waveform at the transmitter outputs of both the smart-to-dumb and the dumb-to-smart links using 650mV signalling, with 100mV induced PLL supply noise. The measured biterror rates for both links are less than 10-14. This confirms that the smart-to-dumb link (periodic phase adjustment) can run as fast as the dumb-to-smart link (continuous phase adjustment), despite the significantly different outer loop bandwidth. Moreover, since the transmitter output and receiver sample time are phase locked by the PLL, the asymmetric link can still run at-speed without periodic calibration, achieving the same performance (less than 10-14 bit-error rate) with only an initial calibration process. Figure 6 shows the measured timing margins of the link at 2Gb/s, with and without PLL supply noise injected at the dumb-end chip. Due to the receiver offset and clock path mismatch between the data and timing receivers, the phase adjustment of both links are slightly offcenter. The last row of Figure 6 shows the timing margin of a smart 32 32 ×

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Cite this paper

@inproceedings{Chang1998DesignIF, title={Design Issues for the Asymmetric Serial Link Measurement Setup and Results a 2gb/s/pin Cmos Asymmetric Serial Link*}, author={Kun-Yung Ken Chang and William Ellersick and Shang-Tse Chuang and Stefanos Sidiropoulos and Mark Horowitz}, year={1998} }