# Depth-Optimal Quantum Circuit Placement for Arbitrary Topologies

@article{Bhattacharjee2017DepthOptimalQC, title={Depth-Optimal Quantum Circuit Placement for Arbitrary Topologies}, author={Debjyoti Bhattacharjee and Anupam Chattopadhyay}, journal={ArXiv}, year={2017}, volume={abs/1703.08540} }

A significant hurdle towards realization of practical and scalable quantum computing is to protect the quantum states from inherent noises during the computation. [] Key Method We present an Integer Linear Programming (ILP) formulation for achieving minimal logical depth while guaranteeing the nearest neighbor arrangement between the interacting qubits. We substantiate our claim with studies on diverse network topologies and prominent quantum circuit benchmarks.

## 44 Citations

### Swap Minimization in Nearest Neighbour Quantum Circuits: An ILP Formulation

- PhysicsAIRO Springer Series
- 2019

A review of the literature solving approaches for the swap minimization problem in quantum circuits and an integer linear programming formulation for it is proposed and some preliminary results on small test instances are given.

### Generalized swap networks for near-term quantum computing

- PhysicsArXiv
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This work addresses the routing problem for families of quantum circuits defined by a hypergraph wherein each hyperedge corresponds to a potential gate and achieves optimal scaling in the case where gates acting on all $\binom{n}{k}$ sets of qubits are desired.

### A Hardware-Aware Heuristic for the Qubit Mapping Problem in the NISQ Era

- Computer ScienceIEEE Transactions on Quantum Engineering
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Evaluation results on IBM quantum hardware show that the proposed hardware-aware (HA) mapping transition algorithm can outperform the state of the art, both in terms of the number of additional gates and circuit fidelity.

### Mapping Quantum Circuits in IBM Q Devices Using Progressive Qubit Assignment for Global Ordering

- PhysicsNew Generation Computing
- 2022

One major challenge in executing a quantum circuit is the restriction on physical qubit interaction. The elementary gates in a quantum circuit must strictly conform to the hardwareâ€™s qubit couplingâ€¦

### Compiling NCV Quantum Circuits for Nearest Neighbour Realization

- Physics2020 International Conference on Emerging Trends in Information Technology and Engineering (ic-ETITE)
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Quantum computers that are based on superconducting and quantum dots have a fundamental requirement called Nearest Neighbour (NN) constraint satisfaction. They require interacting qubits to beâ€¦

### Qubit Mapping and Routing via MaxSAT

- Computer Science2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO)
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This paper presents a novel approach for optimally solving the qubit mapping and routing problem via a reduction to maximum satisfiability (MAXSAT) and presents two novel relaxation ideas that shrink the size of the MAXSAT constraints by exploiting the structure of a quantum circuit.

### MUQUT: Multi-Constraint Quantum Circuit Mapping on Noisy Intermediate-Scale Quantum Computers

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This work extends the technology mapping flows to simultaneously consider the topology and gate fidelity constraints while keeping logical depth and gate count as optimization objectives and provides a comprehensive problem formulation and multi-tier approach towards solving it.

### Technique for two-dimensional nearest neighbour realisation of quantum circuits using weighted look-ahead

- PhysicsIET Comput. Digit. Tech.
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: Quantum computers that are based on technologies like superconducting and quantum dots impose a physical constraint that requires interacting qubits to be adjacent. The initial placement of qubitsâ€¦

### Tackling the Qubit Mapping Problem for NISQ-Era Quantum Devices

- Computer ScienceASPLOS
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A SWAP-based Bidirectional heuristic search algorithm (SABRE) is proposed, applicable to NISQ devices with arbitrary connections between qubits, which outperforms the best known algorithm with exponential speedup and comparable or better results on various benchmarks.

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- Computer Science2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
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This work extends the technology mapping flows to simultaneously consider the topology and gate fidelity constraints while keeping logical depth and gate count as optimization objectives, and provides a comprehensive problem formulation and multi-tier approach towards solving it.

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