Dependable design technique for system-on-chip


Abstract A technique for highly reliable digital design for two FPGAs under a processor control is presented. Two FPGAs are used in a duplex configuration system design, but better dependability parameters are obtained by the combination of totally self-checking blocks based on a parity predictor. Each FPGA can be reconfigured when a SEU fault is detected… (More)
DOI: 10.1016/j.sysarc.2007.09.003



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@article{Kubalk2008DependableDT, title={Dependable design technique for system-on-chip}, author={Pavel Kubal{\'i}k and Hana Kubatova}, journal={Journal of Systems Architecture - Embedded Systems Design}, year={2008}, volume={54}, pages={452-464} }