Demonstration of chip level writability, endurance and data retention of an entire 8Mb STT-MRAM array

@article{Lee2013DemonstrationOC,
  title={Demonstration of chip level writability, endurance and data retention of an entire 8Mb STT-MRAM array},
  author={Y. J. Lee and Guenole Jan and Y. J. Wang and Keyu Pi and Tom Zhong and R. Y. Tong and Vinh D Lam and Jeffrey Teng and Kenlin Huang and Renren He and Son Lam Le and Terry Torng and J. K. DeBrosse and Tom Maffitt and Chen Long and W. J. Gallagher and Po-Kang Wang},
  journal={2013 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)},
  year={2013},
  pages={1-2}
}
We demonstrate the writability of an entire 8 Mb STT-MRAM chip and present data on the expected endurance and data retention up to 90°C. The chip utilizes a device structure that displays high spin-transfer torque efficiency and proper write-current scaling, down to write pulse width of about 1.5 ns.