Delayed line bus scheme: a low-power bus scheme for coupled on-chip buses

Abstract

This paper presents a comprehensive qualitative and analytical analysis of the effect of relative delay on the dissipated energy of coupled lines. Closed form expressions modeling the effect of relative delay on the dissipated energy, and the Miller coupling factor, MCF, are also presented. Skewing the worst switching case is shown to provide up to 50… (More)
DOI: 10.1145/1013235.1013257

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Cite this paper

@article{Ghoneima2004DelayedLB, title={Delayed line bus scheme: a low-power bus scheme for coupled on-chip buses}, author={Maged Ghoneima and Yehea I. Ismail}, journal={Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758)}, year={2004}, pages={66-69} }