Delay locked loop with linear delay element

@article{Jovanovic2005DelayLL,
  title={Delay locked loop with linear delay element},
  author={Goran S. Jovanovic and Mile K. Stojcev and Dragana Krstic},
  journal={TELSIKS 2005 - 2005 uth International Conference on Telecommunication in ModernSatellite, Cable and Broadcasting Services},
  year={2005},
  volume={2},
  pages={397-400 vol. 2}
}
Delay locked loops (DLLs) and phase locked loops (PLLs) are used in synchronous digital systems in order to improve timings, i.e. to minimize negative effects of skew and jitter in the clock distribution network. In this paper, we propose an efficient DLL architecture implemented with linear delay element. Linearization is achieved by modifying the classical hardware structures of the bias and charge pump circuits (Y. Moon et al., 2000). Namely, in our proposal both circuits, instead of single… CONTINUE READING