Delay and Power Minimization in VLSI Interconnects with Spatio-Temporal Bus-Encoding Scheme

Abstract

In deep sub-micron (DSM) technology, the shrinking wire sizes and bus widths are leading to increased propagation delay of on-chip interconnects. There are various techniques proposed in the literature such as wire shaping, shielding, coding etc. to minimize the delay on bus lines. This paper proposes a new bus-encoding scheme to minimize delay and energy on interconnect lines. The proposed encoding scheme eliminates crosstalk classes 4, 5 and 6 and worst case delay (normalized) is reduced to 2(1+ lambda), where lambda is technology parameter. Further, detailed analysis is carried out to find out the impact of encoding combined with wire shaping on further delay reduction. Experiments have been carried out at different technology nodes (180, 130, 90 & 65 nm) for various wire lengths (2, 5 & 10 mm) and it is found out that the encoding scheme reduces delay by about 33% to 67% with only encoding and 47% to 68% with encoding combined with wire shaping for different interconnect dimensions. Concerning energy, SPEC'95 bench mark tests have shown that the encoding scheme also contributes to energy reduction by about 15% on an average.

DOI: 10.1109/ISVLSI.2007.35

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Cite this paper

@article{Sainarayanan2007DelayAP, title={Delay and Power Minimization in VLSI Interconnects with Spatio-Temporal Bus-Encoding Scheme}, author={K. S. Sainarayanan and Chittarsu Raghunandan and M. B. Srinivas}, journal={IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07)}, year={2007}, pages={401-408} }