Delay and Energy Consumption Analysis of Conventional SRAM

  title={Delay and Energy Consumption Analysis of Conventional SRAM},
  author={Arash Azizi-Mazreah and Mohammad T. Manzuri Shalmani and Hamid Barati and Ali Akbar Barati},
The energy consumption and delay in read/write operation of conventional SRAM is investigated analytically as well as by simulation. Explicit analytical expressions for the energy consumption and delay in read and write operation as a function of device parameters and supply voltage are derived. The expressions are useful in predicting the effect of parameter changes on the energy consumption and speed as well as in optimizing the design of conventional SRAM. HSPICE simulation in standard 0.25… CONTINUE READING
Highly Cited
This paper has 22 citations. REVIEW CITATIONS

From This Paper

Figures, tables, and topics from this paper.


Publications citing this paper.
Showing 1-8 of 8 extracted citations

Leakage Current Minimization in Deep-Submicron Conventional Single Cell SRAM

2010 International Conference on Recent Trends in Information, Telecommunication and Computing • 2010
View 12 Excerpts
Highly Influenced

Leakage Current Reduction in 6T Single Cell SRAM at 90nm Technology

2010 International Conference on Advances in Computer Engineering • 2010
View 3 Excerpts
Highly Influenced

A 10-T SRAM cell with inbuilt charge sharing for dynamic power reduction

2013 International Conference on Advances in Technology and Engineering (ICATE) • 2013
View 2 Excerpts

New 3D-integrated burst image sensor architectures with in-situ A/D conversion

2013 Conference on Design and Architectures for Signal and Image Processing • 2013
View 1 Excerpt

Performance-driven SRAM macro design with parameterized cell considering layout-dependent effects

2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC) • 2013
View 1 Excerpt


Publications referenced by this paper.
Showing 1-4 of 4 references

A low-power SRAM design using quiet-bitline architecture

2005 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'05) • 2005
View 4 Excerpts
Highly Influenced

A Low-Power SRAM Using Hierarchical Bit Line and Local Sense Amplifiers

B. D. Yang, L. S. Kim
IEEE J. Solid State Circuits, • 2005
View 1 Excerpt

Huang " A Low - Power SRAM Design Using QuietBitline Architecture

S. Y. S. P. Cheng

Similar Papers

Loading similar papers…