An asynchronous unit delay is an n input n output asynchronous sequential circuit in which the present value of the output n-tuple is equal to the value of the input n-tuple prior to the last input change. This paper considers the problem of determining when a fundamental mode flow table is realizable as a feedback-free connection of asynchronous unit delays. It is shown that such a realization exists if and only if the flow table is asynchronous definite, where the asynchronous definite… CONTINUE READING

Sequential circuit synthesis using hazards and delays

Canonical regular expressions J.A. Brzozowski, state graphs for definite events Proc. Symp. on Mathemat minimal feedback loops in order to avoid improper, +12 authorsIRE Trans. Circuit Theory vol. CT-6 pp. 12-25 March ti delays in asynchronous switching circuits

Dept. of Elec. Engrg., Digital System Lab., Princeton been completed before the next input change is made. University, Princeton, N. J., Tech. Rept. 19; June 1962. • 1962