Defect level evaluation in an IC design environment


The purpose of this paper is to present a methodology for the evaluation of the Defect Level in an IC design environment. The methodology is based on the extension of Williams-Brown formula to non equiprobable faults, which are collected from the IC layout, using the information on a typical IC process line defect statistics. The concept of weighted fault… (More)
DOI: 10.1109/43.541448


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@article{Sousa1996DefectLE, title={Defect level evaluation in an IC design environment}, author={Jos{\'e} T. de Sousa and Fernando M. Gonçalves and Jo{\~a}o Paulo Teixeira and Cristoforo Marzocca and Francesco Corsi and Thomas W. Williams}, journal={IEEE Trans. on CAD of Integrated Circuits and Systems}, year={1996}, volume={15}, pages={1286-1293} }