Deep sub-100 nm Ge CMOS devices on Si with the recessed S/D and channel

@article{Wu2014DeepSN,
  title={Deep sub-100 nm Ge CMOS devices on Si with the recessed S/D and channel},
  author={Heng An Wu and Wei Luo and Mengwei Si and Jingyun Zhang and Hong Zhou and Peide D. Ye},
  journal={2014 IEEE International Electron Devices Meeting},
  year={2014},
  pages={16.7.1-16.7.4}
}
We report on comprehensive studies of Ge CMOS devices with the recessed channel and S/D fabricated on a Ge-on-insulator (GeOI) substrate. Both nFETs and pFETs with channel lengths (Lch) from 500 to 20 nm, channel thicknesses (Tch) from 90 to 15 nm, EOTs from 5 to 3 nm, and gate stacks with and without the post oxidation (PO) are investigated. Benefiting from the fully depleted ultra-thin body (FD-UTB) channel with a reasonable interface, a low sub-threshold slope (SS) of 95 mV/dec is obtained… CONTINUE READING
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