Decoupled software pipelining with the synchronization array

  title={Decoupled software pipelining with the synchronization array},
  author={Ram Rangan and Neil Vachharajani and Manish Vachharajani and David I. August},
  journal={Proceedings. 13th International Conference on Parallel Architecture and Compilation Techniques, 2004. PACT 2004.},
Despite the success of instruction-level parallelism (ILP) optimizations in increasing the performance of microprocessors, certain codes remain elusive. In particular, codes containing recursive data structure (RDS) traversal loops have been largely immune to ILP optimizations, due to the fundamental serialization and variable latency of the loop-carried dependence through a pointer-chasing load. To address these and other situations, we introduce decoupled software pipelining (DSWP), a… CONTINUE READING
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