Decimal floating-point antilogarithmic converter based on selection by rounding: algorithm and architecture

@article{Chen2012DecimalFA,
  title={Decimal floating-point antilogarithmic converter based on selection by rounding: algorithm and architecture},
  author={D. Chen and L. Han and S.-B. Ko},
  journal={IET Computers & Digital Techniques},
  year={2012},
  volume={6},
  pages={277-289}
}
This study presents the algorithm and architecture of the decimal floating-point (DFP) antilogarithmic converter, based on the digit-recurrence algorithm with selection by rounding. The proposed approach can compute faithful DFP antilogarithmic results for any one of the three DFP formats specified in the IEEE 754-2008 standard. The proposed architecture is synthesised with an STM 90-nm standard cell library and the results show that the critical path delay and the number of clock cycles of the… CONTINUE READING

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