# Decimal floating-point: algorism for computers

@article{Cowlishaw2003DecimalFA, title={Decimal floating-point: algorism for computers}, author={Michael F. Cowlishaw}, journal={Proceedings 2003 16th IEEE Symposium on Computer Arithmetic}, year={2003}, pages={104-111} }

Decimal arithmetic is the norm in human calculations, and human centric applications must use a decimal floating point arithmetic to achieve the same results. Initial benchmarks indicate that some applications spend 50% to 90% of their time in decimal processing, because software decimal arithmetic suffers a 100/spl times/ to 1000/spl times/ performance penalty over hardware. The need for decimal floating point in hardware is urgent. Existing designs, however, either fail to conform to modern…

## 311 Citations

Performance Evaluation of Decimal Floating-Point Arithmetic

- Computer Science
- 2005

Hardware implementations of decimal floating-point arithmetic operations when implemented on superscalar processors using either software libraries or specialized hardware designs are shown to be one to two orders of magnitude faster than software implementations.

A survey of hardware designs for decimal arithmetic

- Computer ScienceIBM J. Res. Dev.
- 2010

An overview of DFP arithmetic in IEEE 754-2008 is given, processors that provide hardware and instruction set support for decimal arithmetic are described, and a survey of hardware designs for decimal addition, subtraction, multiplication, and division is provided.

Iterative decimal multiplication using binary arithmetic

- Computer Science2011 VII Southern Conference on Programmable Logic (SPL)
- 2011

An iterative decimal multiplier for FPGA that uses binary arithmetic and the results indicate that the proposed iterative multipliers are very competitive when compared to decimal multipliers implemented with direct manipulation of BCD numbers.

A 64-bit Decimal Floating-Point Comparator

- Engineering, Computer ScienceIEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06)
- 2006

The design and implementation of a novel decimal floating point comparator compliant with the current draft revision of the IEEE-754 Standard for floating-point arithmetic is presented, utilizing a novel BCD magnitude comparator with logarithmic delay and it supports 64- bit decimal floating- point numbers.

Parallel decimal multipliers using binary multipliers

- Computer Science2010 VI Southern Programmable Logic Conference (SPL)
- 2010

This paper analyzes the tradeoffs involved in the design of a parallel decimal multiplier, for decimal operands with 8 and 16 digits, using existent coarse-grained embedded binary arithmetic blocks and indicates that the proposed parallel multipliers are very competitive when compared to decimal multipliers implemented with direct manipulation of BCD numbers.

Decimal floating-point division using Newton-Raphson iteration

- Computer ScienceProceedings. 15th IEEE International Conference on Application-Specific Systems, Architectures and Processors, 2004.
- 2004

This work presents an efficient arithmetic algorithm and hardware design for decimal floating-point division that uses an optimized piecewise linear approximation, a modified Newton-Raphson iteration, a specialized rounding technique, and a simplified combined decimal incrementer/decrementer.

Decimal floating-point division using Newton-Raphson iteration

- Computer Science
- 2004

This work presents an efficient arithmetic algorithm and hardware design for decimal floating-point division that uses an optimized piecewise linear approximation, a modified Newton-Raphson iteration, a specialized rounding technique, and a simplified combined decimal incrementer/decrementer.

Decimal floating-point square root using Newton-Raphson iteration

- Computer Science2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)
- 2005

This paper presents an efficient arithmetic algorithm and hardware design for decimal floating point square root that uses an optimized piecewise linear approximation, a modified Newton-Raphson iteration, a specialized rounding technique, and a modified decimal multiplier.

Decimal floating-point in z9: An implementation and testing perspective

- Computer Science, EngineeringIBM J. Res. Dev.
- 2007

An overview of this implementation of the newly defined decimal floating-point (DFP) format is presented and some measurement of the performance gained using hardware assists is provided.

Decimal Floating-point Fused Multiply Add with Redundant Number Systems

- Computer Science
- 2013

A high performance decimal floatingpoint fused multiply-add (DFMA) with redundant internal encodings was proposed, and the superiority of redundant number systems in stand-alone decimal fixed-point addition and multiplication has been proved by the synthesis results.

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