Decimal floating-point: algorism for computers

@article{Cowlishaw2003DecimalFA,
  title={Decimal floating-point: algorism for computers},
  author={Michael F. Cowlishaw},
  journal={Proceedings 2003 16th IEEE Symposium on Computer Arithmetic},
  year={2003},
  pages={104-111}
}
  • M. Cowlishaw
  • Published 15 June 2003
  • Computer Science
  • Proceedings 2003 16th IEEE Symposium on Computer Arithmetic
Decimal arithmetic is the norm in human calculations, and human centric applications must use a decimal floating point arithmetic to achieve the same results. Initial benchmarks indicate that some applications spend 50% to 90% of their time in decimal processing, because software decimal arithmetic suffers a 100/spl times/ to 1000/spl times/ performance penalty over hardware. The need for decimal floating point in hardware is urgent. Existing designs, however, either fail to conform to modern… 
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References

SHOWING 1-10 OF 67 REFERENCES
A decimal floating-point specification
TLDR
This paper proposes a decimal format which meets the requirements of existing standards for decimal arithmetic and is efficient for hardware implementation, in the hope that designers will consider providing decimal arithmetic in future microprocessors and that future decimal software specifications will consider hardware efficiencies.
Applications of Redundant Number Representations to Decimal Arithmetic
TLDR
The hardware required for the implementation of the basic operations of addition, subtraction, multiplication and division are described and the properties of floating-point arithmetic based on a redundant number representation are investigated.
Desirable floating-point arithmetic and elementary functions for numerical computation
  • T. E. Hull
  • Computer Science
    1978 IEEE 4th Symposium onomputer Arithmetic (ARITH)
  • 1978
TLDR
The purpose of this paper is to summarize proposed specifications for floating-point arithmetic and elementary functions, which are intended to be entirely at the level of a programming language such as Fortran.
CADAC: A Controlled-Precision Decimal Arithmetic Unit
TLDR
The design of an arithmetic unit called CADAC (clean arithmetic with decimal base and controlled precision) is described, which combines both complex and interval arithmetic at the level of a programming language such as Fortran or PL/I.
Compatible number representations
  • R. A. Keir
  • Computer Science
    1975 IEEE 3rd Symposium on Computer Arithmetic (ARITH)
  • 1975
TLDR
A compatible number system for mixed fixed-point and floating-point arithmetic is described in terms of number formats and opcode sequences (for hardwired or microcoded control) to avoid meaningless "normalization" following arithmetic operations.
A unified decimal floating-point architecture for the support of high-level languages
  • F. Ris
  • Computer Science
    SGNM
  • 1976
This paper summarizes a proposal for a decimal floating-point arithmetic interface for the support of high-level languages, consisting both of the arithmetic operations observed by application
Toward an ideal computer arithmetic
TLDR
A new computer arithmetic is described, intended that the language facilities be sufficient for describing numerical processes one might want to implement, while at the same time being simple to use, and implementable in a reasonably efficient manner.
Storage-efficient representation of decimal data
TLDR
Two BCD digits can be compressed optimally and reversibly into 7 bits, and three digits into 10 bits, by a very simple algorithm based on the fixed-length combination of two variable field-length encodings.
Decimal shifting for an exact floating point representation
EASIAC, A Pseudo-Computer
TLDR
A new computer was needed: one designed to make programming easier, at the cost of some of MIDAC's speed and capacity plus two or three man-months of programming time EASIAC, was realized as a translationinterpretation program in MIDAC.
...
1
2
3
4
5
...