Decimal floating-point: algorism for computers
@article{Cowlishaw2003DecimalFA, title={Decimal floating-point: algorism for computers}, author={Michael F. Cowlishaw}, journal={Proceedings 2003 16th IEEE Symposium on Computer Arithmetic}, year={2003}, pages={104-111} }
Decimal arithmetic is the norm in human calculations, and human centric applications must use a decimal floating point arithmetic to achieve the same results. Initial benchmarks indicate that some applications spend 50% to 90% of their time in decimal processing, because software decimal arithmetic suffers a 100/spl times/ to 1000/spl times/ performance penalty over hardware. The need for decimal floating point in hardware is urgent. Existing designs, however, either fail to conform to modern…
311 Citations
Performance Evaluation of Decimal Floating-Point Arithmetic
- Computer Science
- 2005
Hardware implementations of decimal floating-point arithmetic operations when implemented on superscalar processors using either software libraries or specialized hardware designs are shown to be one to two orders of magnitude faster than software implementations.
A survey of hardware designs for decimal arithmetic
- Computer ScienceIBM J. Res. Dev.
- 2010
An overview of DFP arithmetic in IEEE 754-2008 is given, processors that provide hardware and instruction set support for decimal arithmetic are described, and a survey of hardware designs for decimal addition, subtraction, multiplication, and division is provided.
Iterative decimal multiplication using binary arithmetic
- Computer Science2011 VII Southern Conference on Programmable Logic (SPL)
- 2011
An iterative decimal multiplier for FPGA that uses binary arithmetic and the results indicate that the proposed iterative multipliers are very competitive when compared to decimal multipliers implemented with direct manipulation of BCD numbers.
A 64-bit Decimal Floating-Point Comparator
- Engineering, Computer ScienceIEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06)
- 2006
The design and implementation of a novel decimal floating point comparator compliant with the current draft revision of the IEEE-754 Standard for floating-point arithmetic is presented, utilizing a novel BCD magnitude comparator with logarithmic delay and it supports 64- bit decimal floating- point numbers.
Parallel decimal multipliers using binary multipliers
- Computer Science2010 VI Southern Programmable Logic Conference (SPL)
- 2010
This paper analyzes the tradeoffs involved in the design of a parallel decimal multiplier, for decimal operands with 8 and 16 digits, using existent coarse-grained embedded binary arithmetic blocks and indicates that the proposed parallel multipliers are very competitive when compared to decimal multipliers implemented with direct manipulation of BCD numbers.
Decimal floating-point division using Newton-Raphson iteration
- Computer ScienceProceedings. 15th IEEE International Conference on Application-Specific Systems, Architectures and Processors, 2004.
- 2004
This work presents an efficient arithmetic algorithm and hardware design for decimal floating-point division that uses an optimized piecewise linear approximation, a modified Newton-Raphson iteration, a specialized rounding technique, and a simplified combined decimal incrementer/decrementer.
Decimal floating-point division using Newton-Raphson iteration
- Computer Science
- 2004
This work presents an efficient arithmetic algorithm and hardware design for decimal floating-point division that uses an optimized piecewise linear approximation, a modified Newton-Raphson iteration, a specialized rounding technique, and a simplified combined decimal incrementer/decrementer.
Decimal floating-point square root using Newton-Raphson iteration
- Computer Science2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)
- 2005
This paper presents an efficient arithmetic algorithm and hardware design for decimal floating point square root that uses an optimized piecewise linear approximation, a modified Newton-Raphson iteration, a specialized rounding technique, and a modified decimal multiplier.
Decimal floating-point in z9: An implementation and testing perspective
- Computer Science, EngineeringIBM J. Res. Dev.
- 2007
An overview of this implementation of the newly defined decimal floating-point (DFP) format is presented and some measurement of the performance gained using hardware assists is provided.
Decimal Floating-point Fused Multiply Add with Redundant Number Systems
- Computer Science
- 2013
A high performance decimal floatingpoint fused multiply-add (DFMA) with redundant internal encodings was proposed, and the superiority of redundant number systems in stand-alone decimal fixed-point addition and multiplication has been proved by the synthesis results.
References
SHOWING 1-10 OF 67 REFERENCES
A decimal floating-point specification
- Computer ScienceProceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001
- 2001
This paper proposes a decimal format which meets the requirements of existing standards for decimal arithmetic and is efficient for hardware implementation, in the hope that designers will consider providing decimal arithmetic in future microprocessors and that future decimal software specifications will consider hardware efficiencies.
Applications of Redundant Number Representations to Decimal Arithmetic
- Computer Science, MathematicsComput. J.
- 1982
The hardware required for the implementation of the basic operations of addition, subtraction, multiplication and division are described and the properties of floating-point arithmetic based on a redundant number representation are investigated.
Desirable floating-point arithmetic and elementary functions for numerical computation
- Computer Science1978 IEEE 4th Symposium onomputer Arithmetic (ARITH)
- 1978
The purpose of this paper is to summarize proposed specifications for floating-point arithmetic and elementary functions, which are intended to be entirely at the level of a programming language such as Fortran.
CADAC: A Controlled-Precision Decimal Arithmetic Unit
- Computer ScienceIEEE Transactions on Computers
- 1983
The design of an arithmetic unit called CADAC (clean arithmetic with decimal base and controlled precision) is described, which combines both complex and interval arithmetic at the level of a programming language such as Fortran or PL/I.
Compatible number representations
- Computer Science1975 IEEE 3rd Symposium on Computer Arithmetic (ARITH)
- 1975
A compatible number system for mixed fixed-point and floating-point arithmetic is described in terms of number formats and opcode sequences (for hardwired or microcoded control) to avoid meaningless "normalization" following arithmetic operations.
A unified decimal floating-point architecture for the support of high-level languages
- Computer ScienceSGNM
- 1976
This paper summarizes a proposal for a decimal floating-point arithmetic interface for the support of high-level languages, consisting both of the arithmetic operations observed by application…
Toward an ideal computer arithmetic
- Computer Science1987 IEEE 8th Symposium on Computer Arithmetic (ARITH)
- 1987
A new computer arithmetic is described, intended that the language facilities be sufficient for describing numerical processes one might want to implement, while at the same time being simple to use, and implementable in a reasonably efficient manner.
Storage-efficient representation of decimal data
- Computer ScienceCACM
- 1975
Two BCD digits can be compressed optimally and reversibly into 7 bits, and three digits into 10 bits, by a very simple algorithm based on the fixed-length combination of two variable field-length encodings.
EASIAC, A Pseudo-Computer
- Computer ScienceJACM
- 1956
A new computer was needed: one designed to make programming easier, at the cost of some of MIDAC's speed and capacity plus two or three man-months of programming time EASIAC, was realized as a translationinterpretation program in MIDAC.